MC14001B Series
B−Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
•
•
•
•
•
•
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
Symbol
V
I
The B Series logic gates are constructed with P and N channel
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Schottky TTL Load Over the Rated Temperature Range.
Protection on MC14011B and MC14081B
B Suffix Devices
in
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low−power TTL Loads or One Low−power
Double Diode Protection on All Inputs Except: Triple Diode
Pin−for−Pin Replacements for Corresponding CD4000 Series
Pb−Free Packages are Available
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
SS
SS
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
should be constrained
± 10
500
260
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
MC14001B
MC14011B
MC14023B
MC14025B
MC14071B
MC14073B
MC14081B
MC14082B
Device
(Note: Microdot may be in either location)
xx
A
WL, L
YY, Y
WW, W
G or G
ORDERING INFORMATION
DEVICE INFORMATION
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Triple 3−Input NAND Gate
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
Quad 2−Input AND Gate
Dual 4−Input AND Gate
CASE 948G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
CASE 751A
SOEIAJ−14
TSSOP−14
DT SUFFIX
CASE 646
CASE 965
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−14
SOIC−14
Publication Order Number:
Description
14
1
14
14
1
1
DIAGRAMS
MC140xxBCP
AWLYYWWG
14
MARKING
1
MC140xxB
MC14001B/D
AWLYWW
ALYWG
140xxBG
ALYWG
0xxB
14
G