IDT72211 IDT [Integrated Device Technology], IDT72211 Datasheet - Page 2

• Manufacturer Part Number: IDT72211
• Description: CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
PIN CONFIGURATION
PIN DESCRIPTIONS
D
RS
WCLK
WEN1
WEN2/
Q
RCLK
REN1
REN2
OE
EF
PAE
PAF
FF
V
GND
Symbol
CC
0
0
-D
-Q
8
8
REN1
RCLK
REN2
LD
GND
PAF
PAE
D
D
INDEX
1
0
Data Inputs
Reset
Write Clock
Write Enable 1
Write Enable 2/
Load
Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
1
2
3
4
5
6
7
8
Name
32 31 30
9 10 11 12 13 14 15
TOP VIEW
TQFP
29 28
PR32-1
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
27 26 25
Data inputs for a 9-bit bus.
When
FF
power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
If the FIFO is configured to have programmable flags,
When
the FIFO is configured to have two write enables,
HIGH to write data into the FIFO. Data will not be written into the FIFO if the
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables,
data into the FIFO. Data will not be written into the FIFO if the
Data outputs for a 9-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
asserted.
When
of RCLK. Data will not be read from the FIFO if the
When
of RCLK. Data will not be read from the FIFO if the
When
high-impedance state.
When
EF
The default offset at reset is Empty+7.
When
One +5 volt power supply pin.
One 0 volt ground pin.
ured to have programmable flags, WEN2/
offsets.
When
When
default offset at reset is Full-7.
HIGH, the FIFO is not full.
and
is HIGH, the FIFO is not empty.
is HIGH at reset, this pin operates as a second write enable. If WEN2/
16
RS
WEN1
REN1
REN1
OE
EF
PAE
FF
PAF
PAF
24
23
22
21
20
19
18
17
is LOW, the FIFO is full and further data writes into the input are inhibited. When
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
is set LOW, internal read and write pointers are set to the first location of the RAM array,
is LOW, the data output bus is active. If
is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
2655 drw 02a
go HIGH, and
and
and
is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
WEN2/LD
WEN1
WCLK
V
Q
Q
Q
Q
CC
REN2
REN2
8
7
6
5
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
PAE
FF
5.07
is synchronized to WCLK.
PAF
and
EF
EF
is synchronized to WCLK.
WEN1
PAE
go LOW. A reset is required before an initial WRITE after
is synchronized to RCLK.
Description
LD
REN1
RCLK
REN2
INDEX
GND
PAE
PAF
is synchronized to RCLK.
must be LOW and WEN2 must be HIGH to write
OE
is held LOW to write or read the programmable flag
D
D
1
0
WEN1
OE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EF
EF
5
6
7
8
9
10
11
12
13
is HIGH, the output data bus will be in a
WEN1
14 15 16 17 18 19 20
is LOW.
is LOW.
4
must be LOW and WEN2 must be
3
LCC/PLCC
TOP VIEW
is the only write enable pin.
2
L32-1
FF
J32-1
1
is LOW. If the FIFO is config-
32 31 30
REN1
LD
29
28
27
26
25
24
23
22
21
FF
is LOW at reset,
and
is LOW.
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
REN2
CC
2655 drw 02
8
7
6
5
are
FF
2655 tbl 01
is
2