TS80C31X2-LCAB TEMIC [TEMIC Semiconductors], TS80C31X2-LCAB Datasheet
TS80C31X2-LCAB
Related parts for TS80C31X2-LCAB
TS80C31X2-LCAB Summary of contents
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... The TS80C31X2 retains all features of the TEMIC TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscilator and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel multiprocessor communication (EUART) and a X2 speed improvement mechanism ...
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... TS80C31X2 3. Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN CPU EA ( (1) (1) RAM EUART 128x8 C51 CORE IB-bus Timer 0 INT Parallel I/O Ports & Ext. Bus Ctrl Timer 1 Port 0 Port 1 Port 2 Port 3 (1) (1) (1) (1) (1): Alternate function of Port 3 Preliminary Rev Mar. 19, 1999 ...
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... SFR Mapping The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3 Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1 Serial I/O port registers: SADDR, SADEN, SBUF, SCON ...
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... TS80C31X2 5. Pin Configuration P1 VCC 39 P1.1 2 P0.0 38 P1.2 P0 P0.2 P1.3 4 P0.3 P1 P0 P1.6 P0 P1.7 P0.7 RST P3.0/RxD 10 31 PDIL40 ALE P3.1/TxD PSEN P3.2/INT0 29 P3.3/INT1 P2 P2.6 27 P3.4/ P3.5/T1 P2.4 P3.6/ P2 P3.7/RD P2.2 18 XTAL2 23 P2 XTAL1 20 21 P2.0 VSS 44 P1.5 1 P1.6 2 P1.7 3 RST 4 P3.0/RxD 5 NIC* 6 P3.1/TxD 7 8 P3.2/INT0 P3 ...
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... External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations. I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. O Crystal 2: Output from the inverting oscillator amplifier Preliminary TS80C31X2 permits a power-on reset SS CC. 5 ...
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... The ONCE mode. Enhanced UART 6.1 X2 Feature The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). ...
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... For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. Rev Mar. 19, 1999 X2 Mode Figure 2. Mode Switching Waveforms Preliminary TS80C31X2 STD Mode 7 ...
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... TS80C31X2 CKCON - Clock Control Register (8Fh Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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... There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3 DPS AUXR1(A2H) Rev Mar. 19, 1999 DPTR1 DPTR0 DPH(83H) DPL(82H) Figure 3. Use of Dual Pointer Preliminary TS80C31X2 External Data Memory 9 ...
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... TS80C31X2 Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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... Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. Rev Mar. 19, 1999 ; address of SOURCE ; switch data pointers ; address of DEST ; switch data pointers ; get a byte from SOURCE ; increment SOURCE address ; switch data pointers ; write the byte to DEST ; increment DEST address ; check for 0 terminator ; (optional) restore DPS Preliminary TS80C31X2 11 ...
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... TS80C31X2 6.3 TS80C31X2 Serial I/O Port The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates ...
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... NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). Rev Mar. 19, 1999 Data byte bit Figure 5. UART Timings in Mode Start Data byte bit Preliminary TS80C31X2 D6 D7 Stop bit Ninth Stop bit bit 13 ...
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... TS80C31X2 6.3.3 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. ...
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... SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable Rev Mar. 19, 1999 Preliminary TS80C31X2 ...
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... TS80C31X2 SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection ...
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... Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. Rev Mar. 19, 1999 Table 6. PCON Register POF GF1 GF0 Description Preliminary TS80C31X2 IDL 17 ...
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... TS80C31X2 6.4 Interrupt System The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Figure 7. INT0 IE0 TF0 INT1 IE1 TF1 RI TI Individual Enable Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 8 ...
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... Set to enable external interrupt 0. Reset Value = 0XX0 0000b Bit addressable Rev Mar. 19, 1999 Table 7. Priority Level Bit Values IP Table 8. IE Register ET1 Description Table 9. IP Register Preliminary TS80C31X2 Interrupt Level Priority 0 (Lowest (Highest EX1 ET0 EX0 19 ...
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... TS80C31X2 IP - Interrupt Priority Register (B8h Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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... Table 10. IPH Register PSH PT1H PX1H Description PS Priority Level 0 Lowest Highest PT1 Priority Level 0 Lowest Highest PX1 Priority Level 0 Lowest Highest PT0 Priority Level 0 Lowest Highest PX0 Priority Level 0 Lowest Highest Preliminary TS80C31X2 1 0 PT0H PX0H 21 ...
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... In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C31X2 into power-down mode. INT0 INT1 ...
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... Table 11. The state of ports during idle and power-down modes Program Mode ALE Memory Idle External 1 Power Down External 0 Rev Mar. 19, 1999 PSEN PORT0 PORT1 1 Floating Port Data 0 Floating Port Data Preliminary TS80C31X2 PORT2 PORT3 Address Port Data Port Data Port Data 23 ...
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... Pull ALE low while the device is in reset (RST high) and PSEN is high. Hold ALE low as RST is deactivated. While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. ...
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... Reset Value = 00X1 0000b Not bit addressable Rev Mar. 19, 1999 switch-on. A warm start reset occurs while V CC Table 13. PCON Register POF GF1 GF0 Description rises from 0 to its nominal voltage. Can also be set by software. CC Preliminary TS80C31X2 is still applied to CC rises IDL 25 ...
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... TS80C31X2 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Ambiant Temperature Under Bias commercial I = industrial Storage Temperature Voltage Voltage on Any Pin Power Dissipation NOTES S 1. tresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi ...
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... MHz. CC Min Typ -0.5 0 0 ( (5) 90 (5) 10 (5) 13@12 MHz 16@16MHz 5.5@12Mz 7@16 MHz Preliminary TS80C31X2 Max Unit Test Conditions 0 100 A OL 0. 1 0 200 A OL 0.45 ...
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... TS80C31X2 7.3 DC Parameters for Low Voltage + - + Table 15. DC Parameters for Low Voltage Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High Voltage, XTAL1, RST ...
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... RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Test Condition, Idle Mode RST EA XTAL2 (NC) XTAL1 V SS Test Condition, Power-Down Mode CC Preliminary TS80C31X2 All other pins are disconnected. All other pins are disconnected. All other pins are disconnected. 29 ...
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... TS80C31X2 V Figure 12. Clock Signal Waveform for I 7.4 AC Parameters 7.4.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for ...
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... T 18 PXAV T 85 AVIV T 10 PLAZ Rev Mar. 19, 1999 Table 16. Symbol Description Parameter -V -L Min Max Min Max 125 105 145 10 10 Preliminary TS80C31X2 Units ...
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... TS80C31X2 Table 18. AC Parameters for a Variable Clock Symbol Type Standard Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min x PXIX T Max PXIZ T Min PXAV T Max ...
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... ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH Rev Mar. 19, 1999 Table 19. Symbol Description Parameter Preliminary TS80C31X2 33 ...
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... TS80C31X2 Table 20. AC Parameters for a Fix Clock Speed -M (see ordering) Symbol Min Max T 105 RLRH T 105 WLWH T 100 RLDV T 0 RHDX T 15 RHDZ T 160 LLDV T 165 AVDV T 40 110 LLWL T 40 AVWL T 3 QVWX T 145 QVWH T 10 WHQX T 0 RLAZ ...
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... LLWL T QVWX T T LLAX QVWH A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 Preliminary TS80C31X2 -L Units 100 ns 100 100 ...
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... TS80C31X2 7.4.6 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 15. External Data Memory Read Cycle 7.4.7 Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 23. AC Parameters for a Fix Clock Speed -M (see ordering) Symbol ...
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... Rev Mar. 19, 1999 X2 Clock - XLXL T XHQX XHDX VALID VALID VALID VALID Preliminary TS80C31X2 -L Units ns 133 133 SET TI VALID VALID VALID VALID SET RI 37 ...
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... TS80C31X2 7.4.9 External Clock Drive Characteristics (XTAL1) Symbol Parameter T Oscillator Period CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX 7.4.10 External Clock Drive Waveforms V -0 0.7V CC 0.2V -0 CHCL Figure 17. External Clock Drive Waveforms 7 ...
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... PCL OUT DATA SAMPLED FLOAT FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION OLD DATA NEW DATA P1, P2, P3 PINS SAMPLED Figure 20. Clock Waveforms Preliminary TS80C31X2 /I 20mA STATE4 STATE5 PCL OUT DATA ...
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... TS80C31X2 8. Ordering Information TS 80C31X2 -M: VCC: 5V +/- 10% 40 MHz, standard mode 20 MHz, X2 mode -V: VCC: 5V +/- 10% 40 MHz, standard mode 30 MHz, X2 mode -L: VCC: 2 MHz, standard mode 20 MHz, X2 mode TEMIC Semiconductors Code Standard Mode, oscillator frequency Standard Mode, internal frequency X2 Mode, oscillator frequency X2 Mode, internal equivalent frequency ...