MC14012B
Dual 4-Input NAND Gates
P-Channel and N-Channel enhancement mode devices in a single
monolithic structure (Complementary MOS). Their primary use is
where low power dissipation and/or high noise immunity is desired.
Features
•
•
•
•
•
•
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2007
Symbol
V
I
The MC14012B dual 4-input NAND gates are constructed with
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
in
in
Schottky TTL Load Over the Rated Temperature Range
Suffix Devices
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low-Power TTL Loads or One Low-Power
Double Diode Protection on All Inputs
Pin-for-Pin Replacements for Corresponding CD4000 Series B
Pb-Free Packages are Available
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
D
A
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8-Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
- 0.5 to V
SS
- 0.5 to +18.0
- 55 to +125
- 65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
A
WL, L
YY, Y
WW, W
G
ORDERING INFORMATION
CASE 751A
SOEIAJ-14
CASE 646
CASE 965
P SUFFIX
D SUFFIX
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
F SUFFIX
SOIC-14
PDIP-14
Publication Order Number:
14
1
14
14
1
1
DIAGRAMS
MC14012BCP
AWLYYWWG
MARKING
MC14012B
MC14012B/D
AWLYWW
ALYWG
14012BG