TS80C32X2-LCAR TEMIC [TEMIC Semiconductors], TS80C32X2-LCAR Datasheet
TS80C32X2-LCAR
Related parts for TS80C32X2-LCAR
TS80C32X2-LCAR Summary of contents
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CMOS Microcontroller 0-60 MHz 1. Description TEMIC TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C52X2 retains all features of the TEMIC 80C51 with extended ROM/EPROM capacity ...
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... TS80C52X2 TS80C32X2 TS80C52X2 TS87C52X2 3. Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/V PP ( Table 1. Memory size ROM (bytes) EPROM (bytes (3) (3) (1) ROM RAM /EPROM EUART Timer2 256x8 8Kx8 C51 CORE IB-bus Timer 0 INT Parallel I/O Ports & Ext. Bus ...
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SFR Mapping The Special Function Registers (SFRs) of the TS80C52X2 fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, ...
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TS80C52X2 5. Pin Configuration P1 VCC 39 P1.1 2 P0.0 38 P1.2 P0.1 3 P1.3 37 P0.2 4 P0.3 P1 P0 P1.6 P0 P1.7 P0.7 RST 9 32 ...
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Table 3. Pin Description for 40/44 pin packages PIN NUMBER MNEMONIC DIL LCC VQFP 1 Vss1 P0.0-P0.7 39-32 43-36 37-30 P1.0-P1.7 1-8 2-9 40-44 1 ...
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TS80C52X2 Table 3. Pin Description for 40/44 pin packages PIN NUMBER MNEMONIC ALE/PROG PSEN EA XTAL1 XTAL2 TYPE NAME AND FUNCTION O (I) ...
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TS80C52X2 Enhanced Features In comparison to the original 80C52, the TS80C52X2 implements some new features, which are The X2 option. The Dual Data Pointer. The 4 level interrupt priority system. The power-off flag. The ONCE mode. The ALE disabling. ...
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TS80C52X2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed ...
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CKCON - Clock Control Register (8Fh Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this ...
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TS80C52X2 6.2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will ...
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Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set ...
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TS80C52X2 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 ...
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Timer 2 TS80C52X2 The timer 2 in the is compatible with the timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade ...
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TS80C52X2 XTAL1 F XTAL Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1) 6.3.2 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The input clock increments TL2 at frequency ...
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To start the timer, set TR2 run control bit in T2CON register possible to use timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not ...
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TS80C52X2 T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 ...
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T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read ...
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TS80C52X2 6.4 TS80C52X2 Serial I/O Port The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter ...
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Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, ...
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TS80C52X2 6.4.3 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide ...
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Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that ...
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TS80C52X2 SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when ...
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PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 ...
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TS80C52X2 6.5 Interrupt System The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 9. INT0 ...
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IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority ...
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TS80C52X2 IP - Interrupt Priority Register (B8h PT2 Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from ...
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IPH - Interrupt Priority High Register (B7h PT2H Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from ...
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TS80C52X2 6.6 Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to ...
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Table 14. The state of ports during idle and power-down modes Program Mode ALE Memory Idle Internal 1 Idle External 1 Power Down Internal 0 Power Down External 0 * Port 0 can force a "zero" level. A "one" will ...
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TS80C52X2 6.8 ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C52X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C52X2; the following sequence ...
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Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V the device and could be generated for example by ...
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TS80C52X2 6.10 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...
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TS80C52X2 7.1 ROM Structure The TS80C52X2 devices are divided in three different arrays: the code array ...
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TS80C52X2 8. TS87C52X2 8.1 EPROM Structure The TS87C52X2 is divided in two different arrays: the code array ...
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Signature bytes The TS80/87C52X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 9. 8.3 EPROM Programming 8.3.1 Set-up modes In order to program and verify the EPROM or to read the ...
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TS80C52X2 PROGRAM SIGNALS* CONTROL SIGNALS MHz * See Table 31. for proper value on these inputs Figure 11. Set-Up Modes Configuration 8.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and ...
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The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. Programming Cycle A0-A12 D0-D7 ALE/PROG 12.75V 5V EA/VPP 0V Control signals Figure 12. Programming and Verification Signal’s ...
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... Location 30h 31h 60h 60h 60h 61h 38 Table 21. Signature Bytes Content Contents 58h Manufacturer Code: TEMIC 57h Family Code: C51 X2 2Dh Product name: TS80C52X2 ADh Product name: TS87C52X2 20h Product name: TS80C32X2 FFh Product revision number Preliminary Comment Rev Jan. 25, 1999 ...
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Electrical Characteristics 10.1 Absolute Maximum Ratings Ambiant Temperature Under Bias commercial I = industrial Storage Temperature Voltage Voltage Voltage on Any Pin ...
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TS80C52X2 10.2 DC Parameters for Standard Voltage + - + Table 22. DC Parameters ...
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DC Parameters for Low Voltage + - + Table 23. DC Parameters for ...
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TS80C52X2 Figure 13. I Figure 14. I Figure 15 RST EA XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS Test Condition, Active Mode ...
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V Figure 16. Clock Signal Waveform for I 10.4 AC Parameters 10.4.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, ...
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TS80C52X2 10.4.2 External Program Memory Characteristics Symbol T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL ...
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Table 26. AC Parameters for a Variable Clock Symbol Type Standard Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min ...
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TS80C52X2 10.4.4 External Data Memory Characteristics Symbol T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ALE to Valid ...
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Table 28. AC Parameters for a Fix Clock Speed -M (see ordering) Symbol Min Max T 105 RLRH T 105 WLWH T 100 RLDV T 0 RHDX T 15 RHDZ T 160 LLDV T 165 AVDV T 40 110 LLWL ...
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TS80C52X2 Table 29. AC Parameters for a Variable Clock Symbol Type Standard Clock T Min RLRH T Min WLWH T Max RLDV T Min x RHDX T Max ...
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External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 19. External Data Memory Read Cycle 10.4.7 Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX ...
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TS80C52X2 Table 32. AC Parameters for a Variable Clock Symbol Type Standard Clock T Min 12 T XLXL T Min QVHX T Min XHQX T Min x XHDX T Max 10 T ...
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EPROM Programming and Verification Characteristics 0V Table 33. EPROM Programming Parameters Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current PP 1/T Oscillator Frquency ...
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TS80C52X2 10.4.11 External Clock Drive Characteristics (XTAL1) Symbol Parameter T Oscillator Period CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX 10.4.12 External ...
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For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V 10.4.15 Clock Waveforms Valid in normal clock mode. ...
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TS80C52X2 11. Ordering Information TS 87C52X2 -M: VCC: 5V +/- 10% 40 MHz, standard mode 20 MHz, X2 mode -V: VCC: 5V +/- 10% 40 MHz, standard mode 30 MHz, X2 mode -L: VCC: 2 MHz, ...