TS80C54X2 TEMIC [TEMIC Semiconductors], TS80C54X2 Datasheet
TS80C54X2
Related parts for TS80C54X2
TS80C54X2 Summary of contents
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... Programmable Clock Out and Up/Down Timer/ Counter 2 Hardware Watchdog Timer (One-time enabled with Reset-Out) Asynchronous port reset Rev Aug. 31, 1999 TS80C54X2/C58X2 TS87C54X2/C58X2 The fully static design of the TS80C54/58X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 PDIL40 PLCC44 PQFP44 F1 VQFP44 1.4 TS80C54X2 TS80C58X2 TS87C54X2 TS87C58X2 3. Block Diagram (2) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/V PP (2) RD (2) WR (2) (2) 2 Table 1. Memory size ROM (bytes) 16k 32k 0 0 (2) ROM RAM /EPROM EUART 256x8 16/32Kx8 C51 CORE IB-bus Timer 0 Parallel I/O Ports ...
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... RCAP2H TL2 0000 0000 0000 0000 AUXR1 TL0 TL1 TH0 0000 0000 0000 0000 DPL DPH 0000 0000 2/A 3/B 4/C TS80C54X2/C58X2 TS87C54X2/C58X2 5/D 6/E 7/F TH2 0000 0000 IPH XX00 0000 WDTRST WDTPRG XXXX XXXX XXXX X000 TH1 AUXR CKCON 0000 0000 XXXX XX00 XXXX XXX0 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 5. Pin Configuration P1 P1.1 / T2EX 2 38 P1 P1.7 RST 9 32 P3.0/RxD 10 31 PDIL/ P3.1/TxD P3.2/INT0 CDIL40 29 P3.3/INT1 P3.4/ P3.5/T1 P3.6/ P3.7/RD 18 XTAL2 23 19 XTAL1 VSS 44 P1.5 1 P1.6 2 P1.7 3 RST 4 P3.0/RxD 5 NIC* 6 P3.1/TxD 7 8 P3.2/INT0 P3 ...
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... RD (P3.7): External data memory read strobe P3.4 also receives A14 during TS87C58X2 EPROM Programming. I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to V using only an external capacitor to V TS80C54X2/C58X2 TS87C54X2/C58X2 permits a power-on reset SS CC. 5 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 Table 3. Pin Description for 40/44 pin packages PIN NUMBER MNEMONIC ALE/PROG PSEN EA XTAL1 XTAL2 TYPE NAME AND FUNCTION O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1 mode) the oscillator frequency, and can be used for external timing or clocking ...
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... X2 bit is validated on XTAL1 2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. XTAL1:2 2 XTAL1 F XTAL Rev Aug. 31, 1999 state machine: 6 clock cycles. 0 CPU control 1 F OSC X2 CKCON reg Figure 1. Clock Generation Diagram TS80C54X2/C58X2 TS87C54X2/C58X2 : 7 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) ...
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... Set to select 6 clock periods per machine cycle (X2 mode, F Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.temic-semi.com) Rev Aug. 31, 1999 Table 4. CKCON Register Description TS80C54X2/C58X2 TS87C54X2/C58X2 2). OSC XTAL =F ) ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 6.2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 5 ...
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... Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. Rev Aug. 31, 1999 Table 5. AUXR1: Auxiliary Register GF3 Description TS80C54X2/C58X2 TS87C54X2/C58X2 DPS 11 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE 0003 05A2 INC AUXR1 0005 90A000 MOV DPTR,#DEST ...
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... The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution. Rev Aug. 31, 1999 is compatible with the timer 2 in the 80C52. /12 (timer operation) or external pin T2 (counter operation) OSC TS80C54X2/C58X2 TS87C54X2/C58X2 13 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 XTAL1 F XTAL Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1) 6.3.2 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5.) . The input clock increments TL2 at frequency F At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts ...
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... RCAP2H and RCAP2L registers. XTAL1 (: mode) T2 T2EX Rev Aug. 31, 1999 :2 TR2 T2CON reg TL2 (8-bit) RCAP2L (8-bit) Toggle Q D T2OE T2MOD reg EXF2 T2CON reg EXEN2 T2CON reg Figure 5. Clock-Out Mode C/ TS80C54X2/C58X2 TS87C54X2/C58X2 TH2 (8-bit) OVERFLOW RCAP2H (8-bit) TIMER 2 INTERRUPT 15 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. ...
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... Set to program P1.0/T2 as clock output. Down Counter Enable bit 0 DCEN Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable Rev Aug. 31, 1999 Table 7. T2MOD Register Description TS80C54X2/C58X2 TS87C54X2/C58X2 T2OE DCEN 17 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 6.4 TS80C54/58X2 Serial I/O Port The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and ...
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... NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). Rev Aug. 31, 1999 Start Data byte bit Figure 7. UART Timings in Mode Start Data byte bit TS80C54X2/C58X2 TS87C54X2/C58X2 D6 D7 Stop bit Ninth Stop bit bit 19 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 6.4.3 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. ...
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... SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable Rev Aug. 31, 1999 TS80C54X2/C58X2 TS87C54X2/C58X2 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection ...
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... Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. Rev Aug. 31, 1999 Table 9. PCON Register POF GF1 Description TS80C54X2/C58X2 TS87C54X2/C58X2 GF0 PD IDL 23 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 6.5 Interrupt System The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 9. INT0 IE0 TF0 INT1 IE1 TF1 RI TI TF2 ...
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... Clear to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0X00 0000b Bit addressable Rev Aug. 31, 1999 Table 10. Priority Level Bit Values IP Table 11. IE Register ET1 Description TS80C54X2/C58X2 TS87C54X2/C58X2 Interrupt Level Priority 0 (Lowest (Highest EX1 ET0 EX0 25 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 IP - Interrupt Priority Register (B8h PT2 Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Timer 2 overflow interrupt Priority bit ...
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... PT2 Priority Level 0 Lowest Highest PS Priority Level 0 Lowest Highest PT1 Priority Level 0 Lowest Highest PX1 Priority Level 0 Lowest Highest PT0 Priority Level 0 Lowest Highest PX0 Priority Level 0 Lowest Highest TS80C54X2/C58X2 TS87C54X2/C58X2 PX1H PT0H PX0H 27 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 6.6 Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle ...
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... Rev Aug. 31, 1999 PSEN PORT0 1 1 Port Data Floating 0 0 Port Data Floating TS80C54X2/C58X2 TS87C54X2/C58X2 PORT1 PORT2 PORT3 Port Data Port Data Port Data Port Data Address Port Data Port Data Port Data Port Data Port Data Port Data ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 6.8 Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H ...
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... MHz machine cycles, 131 MHz machine cycles, 262 MHz machine cycles, 542 MHz machine cycles, 1. MHz machine cycles, 2. MHz TS80C54X2/C58X2 TS87C54X2/C58X2 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 TM 6.9 ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C54/58X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C54/58X2; the following sequence must be exercised: Pull ALE low while the device is in reset (RST high) and PSEN is high. ...
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... Reset Value = 00X1 0000b Not bit addressable Rev Aug. 31, 1999 switch-on. A warm start reset occurs while V CC Table 18. PCON Register POF GF1 Description rises from 0 to its nominal voltage. Can also be set by software. CC TS80C54X2/C58X2 TS87C54X2/C58X2 is still applied to CC rises GF0 PD IDL 33 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 6.11 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches ...
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... No program lock features enabled. Code verify will still be encrypted by the encryption U array if programmed. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching U code bytes from internal memory sampled and latched on reset. TS80C54X2/C58X2 TS87C54X2/C58X2 35 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 8. TS87C54/58X2 EPROM 8.1 EPROM Structure The TS87C54/58X2 EPROM is divided in two different arrays: the code array 16/32 Kbytes. the encryption array bytes. In addition a third non programmable array is implemented: the signature array bytes. 8.2 EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. ...
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... Program Lock bit 3 1 Rev Aug. 31, 1999 Table 22. EPROM Set-Up Modes ALE/ EA/ PSEN P2.6 PROG VPP 0 12.75V 12.75V 12.75V 1 0 12.75V 1 0 12.75V 1 TS80C54X2/C58X2 TS87C54X2/C58X2 P2.7 P3.3 P3.6 P3 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 PROGRAM SIGNALS* CONTROL SIGNALS MHz * See Table 31. for proper value on these inputs 8.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from program the TS80C54/58X2 the following sequence must be exercised: Step 1: Activate the combination of control signals ...
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... If an application subjects the device to this type of exposure suggested that an opaque label be placed over the window. Rev Aug. 31, 1999 Read/Verify Cycle Data In 100 s TS80C54X2/C58X2 TS87C54X2/C58X2 Data Out 2 rating for 30 minutes distance 39 ...
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... Table 23. Signature Bytes Content Contents 58h Manufacturer Code: TEMIC 57h Family Code: C51 X2 37h Product name: TS80C58X2 B7h Product name: TS87C58X2 3Bh Product name: TS80C54X2 BBh Product name: TS87C54X2 FFh Product revision number Comment Rev Aug. 31, 1999 ...
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... Ports are disconnected, Port 0 is tied to FFh Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. Rev Aug. 31, 1999 ( - - 150 TS80C54X2/C58X2 TS87C54X2/C58X2 41 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 10.3 DC Parameters for Standard Voltage + - + Table 24. DC Parameters in Standard Voltage Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High Voltage, XTAL1, RST ...
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... V to 5 MHz 2 5 MHz. CC Min Typ -0.5 0 0 (6) ( (5) 90 (5) 20 (5) 10 TS80C54X2/C58X2 TS87C54X2/C58X2 Max Unit Test Conditions 3 + 0.6 Freq (MHz 5.5 V @12MHz 10.2 CC @16MHz 12.6 0.25+0.3Freq (MHz @12MHz 3.9 @16MHz 5.1 Max Unit Test Conditions 0 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 Symbol Parameter I Power Supply Current Maximum values (7) mode: idle NOTES 1. I under reset is measured with all output pins disconnected; XTAL1 driven with 0.5V; XTAL2 N.C RST = Port Idle I is measured with all output pins disconnected; XTAL1 driven with T CC N.C ...
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... RST EA (NC) XTAL2 XTAL1 V SS Test Condition, Power-Down Mode CC V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CLCH CHCL 5ns. CLCH CHCL Tests in Active and Idle Modes CC TS80C54X2/C58X2 TS87C54X2/C58X2 All other pins are disconnected. All other pins are disconnected. All other pins are disconnected. 45 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 10.5 AC Parameters 10.5.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. ...
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... Min Max Min Max Min TS80C54X2/C58X2 TS87C54X2/C58X2 -L -L Units X2 mode standard mode 20 MHz 30 MHz Max Min Max 122 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 Table 30. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min x PXIX T Max PXIZ T Max ...
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... ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH Rev Aug. 31, 1999 Table 31. Symbol Description Parameter TS80C54X2/C58X2 TS87C54X2/C58X2 49 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 Table 32. AC Parameters for a Fix Clock Speed -M 40 MHz Symbol Min Max T 130 RLRH T 130 WLWH T 100 RLDV T 0 RHDX T 30 RHDZ T 160 LLDV T 165 AVDV T 50 100 LLWL T 75 AVWL T 10 QVWX T 160 QVWH T 15 WHQX T 0 RLAZ ...
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... LLWL T QVWX T T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 TS80C54X2/C58X2 TS87C54X2/C58X2 -L Units ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 10.5.6 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 20. External Data Memory Read Cycle 10.5.7 Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 35. AC Parameters for a Fix Clock Speed -M 40 MHz ...
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... 133 133 XLXL T XHQX XHDX VALID VALID VALID VALID TS80C54X2/C58X2 TS87C54X2/C58X2 -L Units 133 SET TI VALID VALID VALID VALID SET RI 53 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 10.5.9 EPROM Programming and Verification Characteristics 0V Table 37. EPROM Programming Parameters Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current PP 1/T Oscillator Frquency CLCL T Address Setup to PROG Low AVGL T PROG Adress Hold after GHAX T Data Setup to PROG Low ...
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... CHCL CLCX T CLCL 0.2V +0.9 CC 0.2V -0 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement CC max for a logic “0”. IL FLOAT -0 LOAD LOAD V +0.1 V LOAD Figure 25. Float Waveforms TS80C54X2/C58X2 TS87C54X2/C58X2 Max Units CHCX T CLCH +0 ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V 10.5.15 Clock Waveforms Valid in normal clock mode mode XTAL2 signal must be changed to XTAL2 divided by two. ...
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... VCC: 2 MHz, X1 mode 20 MHz, X2 mode -E: Samples Part Number TS80C54X2yyy: 16k ROM, yyy is the customer code TS80C58X2yyy: 32k ROM, yyy is the customer code TS87C54X2: 16k OTP EPROM TS87C58X2: 32k OTP EPROM TEMIC Semiconductors (*) Check with TEMIC Sales Office for availability. Ceramic packages (J, K) are available for prototyping, not for volume production. ...
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... TS80C54X2/C58X2 TS87C54X2/C58X2 TS80C54/58zzz ROM -MCA X -MCB X -MCC X -MCE X -VCA X -VCB X -VCC X -VCE X -LCA X -LCB X -LCC X -LCE X -MIA X -MIB X -MIC X -MIE X -VIA X -VIB X -VIC X -VIE X -LIA X -LIB X -LIC X -LIE X -EA -EB -EC -EE -EJ -EK -Ex for samples Tape and Reel available for B, C and E packages ...