IDT72V01 IDT [Integrated Device Technology], IDT72V01 Datasheet - Page 9

• Manufacturer Part Number: IDT72V01
• Description: 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9
OPERATING MODES:
monitored by each system (i.e.
where
For additional information, refer to Tech Note 8: Operating
FIFOs on Full and Empty Boundary Conditions and Tech Note
6: Designing with FIFOs.
Single Device Mode
when the application requirements are for 512/1024/2048/
4096 words or less. IDT72V01/72V02/72V03/72V04 is in a
Single Device Configuration when the Expansion In (
control input is grounded (see Figure 12).
Depth Expansion
to applications when the requirements are for greater than
512/1,024/2,048/4,096 words. Figure 14 demonstrates Depth
Expansion using three IDT72V01/72V02/72V03/72V04s. Any
depth can be attained by adding additional IDT72V01/72V02/
72V03/72V04s. The IDT72V01/72V02/72V03/72V04 oper-
ates in the Depth Expansion mode when the following condi-
tions are met:
1. The first device must be designated by grounding the First
2. All other devices must have
3. The Expansion Out (
4. External logic is needed to generate a composite Full Flag
5. The Retransmit (
FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion
corresponding input control signals of multiple devices. Sta-
tus flags (
A single IDT72V01/72V02/72V03/72V04 may be used
The IDT72V01/72V02/72V03/72V04 can easily be adapted
For additional information, refer to Tech Note 9: Cascading
Word width may be increased simply by connecting the
Load (
the Expansion In (
(
EF
correct composite
not available in the Depth Expansion Mode.
Care must be taken to assure that the appropriate flag is
FF
s and ORing of all
W
) and Empty Flag (
is used;
EF
FL
,
) control input.
FF
and
EF
XI
W
R
is monitored on the device where
HF
RT
XI
FF
) pin of the next device. See Figure 14.
) function and Half-Full Flag (
) can be detected from any one device.
FF
XO
or
EF
s (i.e. all must be set to generate the
) pin of each device must be tied to
EF
). This requires the ORing of all
). See Figure 14.
t
FF
XIS
FL
is monitored on the device
in the high state.
t
XI
FIRST PHYSICAL
LOCATION
WRITE TO
R
Figure 11. Expansion In
is used).
HF
) are
XI
)
5.08
t
XIR
Figure 13 demonstrates an 18-bit word width by using two
IDT72V01/72V02/72V03/72V04s. Any word width can be
attained by adding additional IDT72V01/72V02/72V03/72V04s
(Figure 13).
Bidirectional Operation
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT72V01/72V02/72V03/72V04s
as shown in Figure 16. Both Depth Expansion and Width
Expansion may be used in this mode.
Data Flow-Through
flow-through and write flow-through mode. For the read flow-
through mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (t
edge of
bus until the
bus would go into a three-state mode after t
would have a pulse showing temporary deassertion and then
would be asserted.
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The
the
be asserted again in anticipation of a new data word. On the
rising edge of
line must be toggled when
in the FIFO and to increment the write pointer.
Compound Expansion
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
Applications which require data buffering between two
Two types of flow-through modes are permitted, a read
In the write flow-through mode (Figure 18), the FIFO
The two expansion techniques described above can be
FF
to be deasserted but the
W
, called the first write edge, and it remains on the
t
R
XIS
W
line is raised from low-to-high, after which the
, the new word is loaded in the FIFO. The
FIRST PHYSICAL
READ FROM
LOCATION
FF
COMMERCIAL TEMPERATURE RANGE
is not asserted to write new data
W
WEF
line being low causes it to
2679 drw 13
+ t
A
RHZ
) ns after the rising
ns. The
R
line causes
EF
9
line
W