SST25LF080A-33-4C-S2AE SST [Silicon Storage Technology, Inc], SST25LF080A-33-4C-S2AE Datasheet - Page 10

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SST25LF080A-33-4C-S2AE

Manufacturer Part Number
SST25LF080A-33-4C-S2AE
Description
8 Mbit SPI Serial Flash
Manufacturer
SST [Silicon Storage Technology, Inc]
Datasheet

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EOL Product Data Sheet
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz
is initiated by executing an 8-bit command, 0BH, followed
by address bits [A
remain active low for the duration of the High-Speed-Read
cycle. See Figure 5 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
©2006 Silicon Storage Technology, Inc.
SCK
CE#
FIGURE 5: H
SO
SI
MODE 3
MODE 0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
MSB
0 1 2 3 4 5 6 7 8
IGH
23
-A
-S
0
] and a dummy byte. CE# must
PEED
0B
-R
HIGH IMPEDANCE
EAD
S
EQUENCE
MSB
ADD.
15 16
ADD.
23 24
ADD.
10
IL
or V
31 32
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
8 Mbit density, once the data from address location
0FFFFFH has been read, the next output will be from
address location 000000H.
IH
)
X
39 40
MSB
D
OUT
N
47 48
D
N+1
OUT
8 Mbit SPI Serial Flash
55 56
D
N+2
OUT
63 64
SST25LF080A
D
1248 F05.0
N+3
OUT
S71248-06-EOL
71 72
D
N+4
OUT
80
1/06

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