SST27SF010-70-3C-PHE SST [Silicon Storage Technology, Inc], SST27SF010-70-3C-PHE Datasheet
![no-image](/images/no-image-200.jpg)
SST27SF010-70-3C-PHE
Available stocks
Related parts for SST27SF010-70-3C-PHE
SST27SF010-70-3C-PHE Summary of contents
Page 1
... To meet surface mount and conventional through hole requirements, the SST27SF512 are offered in 32-lead PLCC, 32-lead TSOP , and 28-pin PDIP packages. The SST27SF010/020 are offered in 32-pin PDIP , 32-lead PLCC, and 32-lead TSOP packages. See Figures 1, 2, and 3 for pin assignments. ©2005 Silicon Storage Technology, Inc. ...
Page 2
... SST27SF512 and PGM# pin low for SST27SF010/020 µs. Using the MTP pro- gramming algorithm, the Byte-Programming process con- tinues byte-by-byte until the entire chip has been programmed ...
Page 3
... UNCTIONAL LOCK IAGRAM OF THE Address Buffer CE# OE PGM for SST27SF020 for SST27SF010 ©2005 Silicon Storage Technology, Inc. SST27SF512 X-Decoder SST27SF010/020 X-Decoder Control Logic 3 Data Sheet SuperFlash Memory Y-Decoder I/O Buffers 1152 B2.1 ...
Page 4
... A16 A16 NC 10 A15 11 A12 FIGURE SSIGNMENTS FOR ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 SST27SF512 32-lead PLCC Top View A1 10 ...
Page 5
... The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low OE# Output Enable For SST27SF010/020, to gate the data output buffers during Read operation OE#/V Output Enable/V For SST27SF512, to gate the data output buffers during Read operation and high voltage PP PP ...
Page 6
... IH Program/Erase Inhibit Product Identification can but no other value. IL IH, 2. Device ID = A5H for SST27SF010 and A6H for SST27SF020 Most significant address for SST27SF010 and Note 11.4-12V 11.4-12V PPH H ©2005 Silicon Storage Technology, Inc. ...
Page 7
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
Page 8
... N Endurance END 1 T Data Retention DR 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 C PERATING HARACTERISTICS FOR (T =25°C±5°C) PPH A Limits Min ...
Page 9
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 AC CHARACTERISTICS TABLE 11 EAD YCLE IMING Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time CE# Low to Active Output ...
Page 10
... Recovery Time for Erase Rise Time to 12V during Erase ART Setup Time during Erase A9S Hold Time during Erase A9H 9 ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 T P SST27SF010/020 IMING ARAMETERS FOR 10 Min Max Units 1 µs 1 µs 1 µs 1 µs 50 ...
Page 11
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 ADDRESS CE# OE# HIGH-Z DQ 7-0 FIGURE EAD YCLE IMING ADDRESS (EXCEPT CE# DQ 7-0 V PPH OE#/ PRT V PPH ART FIGURE HIP RASE IMING ©2005 Silicon Storage Technology, Inc. ...
Page 12
... RASE IMING ADDRESS CE# DQ 7-0 HIGH-Z V PPH V DD OE#/ FIGURE YTE ROGRAM IMING ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 SST27SF010/020 IAGRAM FOR ADDRESS VALID DATA VALID T VPS T PRT D SST27SF512 IAGRAM FOR 12 T CEH T VPH ...
Page 13
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 ADDRESS CE# OE 7-0 HIGH-Z V PPH PGM# FIGURE YTE ROGRAM IMING ©2005 Silicon Storage Technology, Inc. ADDRESS VALID DATA VALID T VPS T PRT CES D SST27SF010/020 ...
Page 14
... FIGURE NPUT UTPUT TO DUT FIGURE 10 EST OAD XAMPLE ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 V HT REFERENCE POINTS V LT (0.4 V) for a logic “0”. Measurement reference points for ILT (0.8 V). Input rise and fall times (10 EFERENCE AVEFORMS ...
Page 15
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Start OE#/ PPH Erase 100ms pulse (CE OE#/ Wait for OE#/V PP and A 9 Recovery Time Read Device (CE Compare All bytes to FFH Yes ...
Page 16
... Data Sheet Increment Address No * See Figure 11 FIGURE 13 YTE ROGRAM LGORITHM FOR ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 Start Erase* OE#/ PPH Address = First Location Program 20µs pulse (CE OE#/ Last Address? Yes Wait for OE#/V PP RecoveryTime ...
Page 17
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Address = First Location CE OE Program 20µs pulse Increment Address No * See Figure 12 FIGURE 14 YTE ROGRAM LGORITHM FOR ©2005 Silicon Storage Technology, Inc. Start Erase PPH (PGM ...
Page 18
... Kbit Voltage Range S = 4.5-5.5V Product Series 27 = Many-Time Programmable Flash 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. SST27SF512-70-3C-PG SST27SF512-70-3C-PGE SST27SF010-70-3C-PH SST27SF010-70-3C-PHE SST27SF020-70-3C-PH SST27SF020-70-3C-PHE non-Pb OTP/EPROM replacement with EPROM pinout S71152-11-000 9/05 ...
Page 19
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional .447 Pin #1 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. ...
Page 20
... All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. 32 LEAD HIN MALL UTLINE SST ACKAGE ODE ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 8.10 7.90 1.20 max. (TSOP ACKAGE 1.05 0.95 0.50 BSC 0.27 0.17 0.15 ...
Page 21
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Pin #1 Identifier .075 .065 Base Plane Seating Plane .050 .015 .080 .065 .070 .045 Note: 1. Complies with JEDEC publication 95 MO-015 AH dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). ...
Page 22
... Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32 PIN LASTIC UAL N LINE INS SST ACKAGE ODE ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 1.655 1.645 .200 .170 .150 .120 .100 BSC .022 .016 (PDIP) 22 .625 .600 .550 .530 7˚ 4 PLCS. 0˚ ...
Page 23
... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 TABLE 14 EVISION ISTORY Number 02 • 2002 Data Book 03 • Document Control Release (SST Internal): No technical changes 04 • Corrected I Supervoltage Current for • Corrected the Test Conditions for I 06 • ...