SST29EE010-120-4C-EH SST [Silicon Storage Technology, Inc], SST29EE010-120-4C-EH Datasheet - Page 5

• Manufacturer Part Number: SST29EE010-120-4C-EH
• Description: 1 Megabit (128K x8) Page-Mode EEPROM
• Manufacturer: SST [Silicon Storage Technology, Inc]

1 Megabit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
T
© 2000 Silicon Storage Technology, Inc.
DQ
CE#
OE#
WE#
Vcc
Vss
NC
Symbol
A
ABLE
A
F
F
6
16
-A
IGURE
IGURE
7
-DQ
-A
0
2: P
7
1: P
0
2: P
IN
D
IN
IN
ESCRIPTION
A
Pin Name
Row Address Inputs
Column Address
Data Input/output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
A
Inputs
SSIGNMENTS FOR
DQ0
DQ1
DQ2
V SS
SSIGNMENTS FOR
A16
A15
A12
NC
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
WE#
V CC
Top View
A11
A13
A14
A16
A15
A12
NC
NC
A9
A8
A7
A6
A5
A4
32-Pin
PDIP
32-
32-
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TSOP
P
Functions
To provide memory addresses. Row addresses define a page for a
Write cycle.
Column Addresses are toggled to load page data.
To output data during Read cycles and receive input data during Write
cycles. Data is internally latched during a Write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations
To provide 5-volt supply (± 10%) for the SST29EE010, 3-volt supply
(3.0-3.6V) for the SST29LE010 and 2.7-volt supply (2.7-3.6V) for the
SST29VE010
Unconnected pins.
LASTIC
V CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
DIP
Standard Pinout
S AND
Top View
Die Up
32-
5
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
LEAD
PLCC
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
4
S
3
32-Lead PLCC
Top View
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
32 31 30
304 ILL F01.1
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
304 ILL F02.0
304 PGM T2.0
304-3 6/00
5
6
7
8
13
14
15
16
1
2
3
4
9
10
11
12