DS3231MZ+ MAXIM [Maxim Integrated Products], DS3231MZ+ Datasheet - Page 13

• Manufacturer Part Number: DS3231MZ+
• Manufacturer: MAXIM [Maxim Integrated Products]

BITS 4:3
ESOC
BIT 7
BIT 7
BIT 6
BIT 5
BIT 2
BIT 1
BIT 0
0
ESOC: Enable oscillator. When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is
stopped when the device switches to V
device is powered by V
lator is disabled, all register data is static.
BBSQW: Battery-backed square-wave enable. When set to logic 1 with INTCN = 0 and V
enables the 1Hz square wave. When BBSQW is logic 0, INT/SQW goes high impedance when V
V
CONV: Convert temperature. Setting this bit to 1 forces the temperature sensor to convert the temperature
into digital code and execute the temperature compensate algorithm to update the oscillator’s accuracy. The
device cannot be forced to execute the temperature-compensate algorithm faster than once per second. A
user-initiated temperature conversion does not affect the internal update cycle. The CONV bit remains at a 1
from the time it is written until the temperature conversion is completed, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. See Figure 7 for
more details.
NA: Not applicable. These bits have no affect on the device and can be set to either 0 or 1.
INTCN: Interrupt control. This bit controls the INT/SQW output signal. When the INTCN bit is set to logic 0, a
1Hz square wave is output on INT/SQW. When the INTCN bit is set to logic 1, a match between the timekeep-
ing registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to a logic
1 when power is first applied.
A2IE: Alarm 2 interrupt enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status reg-
ister to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the
A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
A1IE: Alarm 1 interrupt enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status reg-
ister to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the
A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied
PF
BBSQW
. This bit is disabled (logic 0) when power is first applied.
BIT 6
0
CONV
BIT 5
0
CC
, the oscillator is always on regardless of the status of the EOSC bit. When the oscil-
±5ppm, I
BIT 4
NA
1
BAT
. This bit is clear (logic 0) when power is first applied. When the
BIT 3
NA
1
2
C Real-Time Clock
INTCN
BIT 2
1
Control Register (0Eh)
BIT 1
A2IE
0
CC
< V
CC
PF
, this bit
falls below
BIT 0
A1IE
0
.
13