SST34HF32A4-70-4E-L1PE SST [Silicon Storage Technology, Inc], SST34HF32A4-70-4E-L1PE Datasheet
SST34HF32A4-70-4E-L1PE
Related parts for SST34HF32A4-70-4E-L1PE
SST34HF32A4-70-4E-L1PE Summary of contents
Page 1
... The entire flash memory bank can be erased and programmed word-by-word in typically 4 sec- onds for the SST34HF32A4, when using interface features such as Toggle Bit, Data# Polling, or RY/BY# to indicate the CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc. ...
Page 2
... WE# and OE# which minimize power consumption and area. Designed, manufactured, and tested for applications requir- ing low power and small form factor, the SST34HF32A4 are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figure 3 for pin assignments. ...
Page 3
... Silicon Storage Technology, Inc. Preliminary Specifications Flash Chip-Erase Operation The SST34HF32A4 provide a Chip-Erase operation, which allows the user to erase all flash sectors/blocks to the “1” state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence ...
Page 4
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory Preliminary Specifications Flash Write Operation Status Detection The SST34HF32A4 provide one hardware and two soft- ware means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/ Busy# (RY/BY#) pin ...
Page 5
... Hardware Block Protection The SST34HF32A4 provide a hardware block protection which protects the outermost 8 KWord in Bank 1. The block ) 2 is protected when WP# is held low. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors ...
Page 6
... Refer to Table 6 for more details. Product Identification The Product Identification mode identifies the device as the SST34HF32A4 and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by pro- grammers cannot be used on this device because of the shared lines between flash and PSRAM in the multi-chip package ...
Page 7
... PSRAM Read BEF# high, the The PSRAM Read operation of the SST34HF32A4 is con- trolled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the out- puts. BES1# and BES2 are used for PSRAM bank selec- tion ...
Page 8
... Notes: 1. For LS package only: FIGURE 2: Functional Block Diagram ©2006 Silicon Storage Technology, Inc. Address Buffers SuperFlash Memory (Bank 1) SuperFlash Memory (Bank 2) Control Logic 16 Mbit PSRAM Address Buffers WE# = WEF# and/or WES# OE# = OEF# and/or OES# 8 SST34HF32A4 I/O Buffers DQ / 1313 B1.0 S71313-02-000 8/06 ...
Page 9
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 TABLE 3: Dual-Bank Memory Organization ( SST34HF32A4 Block BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 Bank 1 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 ...
Page 10
... 040000H–04FFFFH 030000H–03FFFFH 020000H–02FFFFH 010000H–01FFFFH 000000H–00FFFFH 10 SST34HF32A4 Address Range x16 0A8000H–0AFFFFH 0A0000H–0A7FFFH 098000H–09FFFFH 090000H–097FFFH 088000H–08FFFFH 080000H–087FFFH 078000H–07FFFFH 070000H–077FFFH 068000H–06FFFFH 060000H– ...
Page 11
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 PIN DESCRIPTION FIGURE 3: Pin Assignments for 56-ball LFBGA (8mm x 10mm FIGURE 4: Pin Assignment for 62-Ball LFBGA (8mm x 10mm) ©2006 Silicon Storage Technology, Inc. TOP VIEW (balls facing down) 8 A15 NC NC ...
Page 12
... To output the status of a Program or Erase Operation RY/BY open drain output 10KΩ - 100KΩ pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. Flash only PSRAM only 2.7-3.3V Power Supply to Flash only 2.7-3.3V Power Supply to PSRAM only Unconnected pins 12 SST34HF32A4 T4.0 1313 S71313-02-000 8/06 ...
Page 13
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 TABLE PERATIONAL ODES ,1 Mode BEF# BES1# Full Standby V IH PSRAM Deep Power-down Output Disable Flash Read V IL Flash Write V IL Flash Erase V IL PSRAM Read V IH PSRAM Write V IH Product ...
Page 14
... For SST34HF32A4 the Security ID Address Range is: (x16 mode) = 0FF000H to 0FF087H, (x8 mode) = 000000H to 00010FH SST ID is read at Address Range (x16 mode) = 000000H to 000007H (x8 mode) = 000000H to 0000FFH User ID is read at Address Range (x16 mode) = 000008H to 000087H (x8 mode) = 000100H to 00010FH Lock Status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked ...
Page 15
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 TABLE 7: CFI Q I UERY DENTIFICATION Address Address 2 x16 Mode x8 Mode Data 10H 20H 0051H 11H 22H 0052H 12H 24H 0059H 13H 26H 0002H 14H 28H 0000H 15H 2AH 0000H 16H 2CH 0000H 17H 2EH ...
Page 16
... Bytes = 64 KByte/block (0100H = 256) Sector Information ( Number of sectors 256B = sector size 1023 + 1 = 1024 sectors (03FFH = 1023 256 Bytes = 4 KByte/sector (0010H = 16) = 25° 1. 2.7-3. SST34HF32A4 = 4 MByte) N (00H = not supported) S71313-02-000 T9.2 1313 1 +0. +1.0V DD 8/06 ...
Page 17
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 TABLE 10: DC Operating Characteristics (V Symbol Parameter 1 I Active V Current DD DD Read Flash PSRAM Concurrent Operation 2 Write Flash PSRAM I Standby V Current Reset Current Input Leakage Current LI I Input Leakage Current LIW on WP# pin and RST# pin ...
Page 18
... Test Condition I Minimum Specification Units 10,000 Cycles 100 Years 100 + SST34HF32A4 Units µs µs T11.0 1313 Maximum T12.0 1313 Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T13.0 1313 S71313-02-000 8/06 ...
Page 19
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 AC CHARACTERISTICS TABLE 14: PSRAM Read Cycle Timing Parameters T Read Cycle Time RCS T Address Access Time AAS T Bank Enable Access Time BES T Output Enable Access Time OES T UBS#, LBS# Access Time BYES 1 T BES# to Active Output ...
Page 20
... This parameter does not apply to Chip-Erase operations. ©2006 Silicon Storage Technology, Inc. = 2.7-3.3V DD Min 500 50 Min SST34HF32A4 Max Units µs T16.0 1313 Max Units 10 µs ...
Page 21
... If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance. Because D signals may be in the output state at this time, input signals of reverse polarity must not be applied Most Significant PSRAM Address MSS for SST34HF32A4 MSS 19 FIGURE 6: PSRAM Write Cycle Timing Diagram (WE# Controlled) ©2006 Silicon Storage Technology, Inc. T RCS T AAS ...
Page 22
... Because D signals may be in the output state at this time, input signals of reverse polarity must not be applied Most Significant PSRAM Address MSS for SST34HF32A4 MSS 19 FIGURE 7: PSRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled) ©2006 Silicon Storage Technology, Inc. T WCS T ...
Page 23
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 ADDRESS A 20-0 BEF# OE WE# HIGH-Z DQ 15-0 FIGURE 8: Flash Read Cycle Timing Diagram for Word Mode (For Byte Mode A 555 ADDRESS A 20 WE# T WPH T AS OE# BEF# RY/BY# DQ 15-0 XXAA Note: X can FIGURE 9: Flash WE# Controlled Program Cycle Timing Diagram for Word Mode (For Byte Mode A © ...
Page 24
... Silicon Storage Technology, Inc. 2AA 555 ADDR XX55 XXA0 DATA WORD (ADDR/DATA) , but no other value Address Input OEH DATA# = Address Input SST34HF32A4 VALID 1313 F06.0 T OES DATA DATA# 1313 F07.0 S71313-02-000 8/06 ...
Page 25
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 ADDRESS A 20-0 BEF# T OEH OE# WE FIGURE 12: Flash Toggle Bit Timing Diagram for Word Mode (For Byte Mode A ADDRESS 555 2AA A 20-0 BEF# OE WE# RY/BY# XXAA XX55 DQ 15-0 Note: This device also supports BEF# controlled Chip-Erase operation. ...
Page 26
... BA X XX80 XXAA XX55 XX30 but no other value. IH, = Don’t Care) -1 555 555 2AA SA X XX80 XXAA XX55 XX50 but no other value. IH, = Don’t Care SST34HF32A4 VALID 1313 F10 VALID 1313 F11.0 S71313-02-000 8/06 ...
Page 27
... Three-Byte Sequence For Software ID Entry 555 2AA ADDRESS A 20-0 BEF# OE WE# XXAA DQ 15-0 Note: X can Device ID - 7353H for SST34HF32A4 FIGURE 16: Flash Software ID Entry and Read (For Byte Mode A THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESSES 555 2AA CE# OE WE# DQ XXAA 15-0 ...
Page 28
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory Preliminary Specifications RY/BY RST# BEF#/OE# FIGURE 18: RST# Timing (when no internal operation is in progress) RY/BY# RST# BEF# OE# FIGURE 19: RST# Timing (during Sector- or Block-Erase operation) ©2006 Silicon Storage Technology, Inc. T RHR SST34HF32A4 1313 F13.0 1313 F14.0 S71313-02-000 8/06 ...
Page 29
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 V IHT INPUT? V ILT AC test inputs are driven at V (0.9 V IHT for inputs and outputs are V (0 FIGURE 20: AC Input/Output Reference Waveforms TO DUT FIGURE 21: A Test Load Example ©2006 Silicon Storage Technology, Inc. V REFERENCE POINTS IT ) for a logic “1” and V (0 ...
Page 30
... Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Address/Data Wait for end of Program ( Data# Polling bit, or Toggle bit operation) Program Completed 1313 F17.0 Note: X can but no other value SST34HF32A4 S71313-02-000 8/06 ...
Page 31
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 Internal Timer Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 23: Wait Options ©2006 Silicon Storage Technology, Inc. Toggle Bit Program/Erase Initiated Read byte/word Read same No byte/word No Does DQ 6 match? Yes Program/Erase Completed ...
Page 32
... Load data: XX98H Address: 555H Wait T IDA Read CFI data Note: X can but no other value. IL IH, 32 SST34HF32A4 Software ID Exit/ CFI Exit Command Sequence Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXF0H Address: 555H Wait T IDA ...
Page 33
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 Sec ID Query Entry Command Sequence Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX88H Address: 555H Wait T IDA Read Sec ID FIGURE 25: Software Sec ID/CFI Command Flowcharts ©2006 Silicon Storage Technology, Inc. ...
Page 34
... Load data: XX50H Address Wait T SE Sector erased to FFFFH Note: X can but no other value. IL IH, 34 SST34HF32A4 Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XXAAH Address: 555H ...
Page 35
... Suffix1 SST34HF32x4X- XXX - Valid combinations for SST34HF32A4 SST34HF32A4-70-4E-L1PE SST34HF32A4-70-4E-LSE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. ...
Page 36
... All linear dimensions are in millimeters. 3. Coplanarity: 0. Ball opening size is 0.38 mm (± 0.05 mm) FIGURE 27: 56-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 8mm x 10mm SST Package Code: L1P ©2006 Silicon Storage Technology, Inc. 5.60 8.00 ± 0.20 0.80 1.30 ± 0.10 0.12 0.35 ± 0.05 36 SST34HF32A4 BOTTOM VIEW 5.60 0. 0.45 ± 0.05 ...
Page 37
... Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory SST34HF32A4 TOP VIEW 10.00 ± 0. CORNER SIDE VIEW SEATING PLANE Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. ...