SST49LF004B-33-4C-EI SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-EI Datasheet - Page 11

• Manufacturer Part Number: SST49LF004B-33-4C-EI
• Description: 4 Mbit LPC Firmware Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

4 Mbit LPC Firmware Flash
SST49LF004B
MODE SELECTION
The SST49LF004B flash memory device operates in two
distinct interface modes: the LPC mode and the Parallel
Programming (PP) mode. In LPC mode, communication
between the Host and the SST49LF004B occurs via the 4-
bit I/O communication signals, LAD[3:0], and LFRAME#. In
PP mode, the device is controlled via the 11 addresses,
A
are multiplexed in row and column selected by control sig-
nal R/C# pin. The row addresses are mapped to the lower
internal addresses (A
mapped to the higher internal addresses (A
ure 3, Device Memory Map, for address assignments.
©2003 Silicon Storage Technology, Inc.
10
-A
0
, and 8 I/O, DQ
10-0
7
-DQ
), and the column addresses are
0
, signals. The address inputs
18-11
). See Fig-
11
LPC MODE
Device Operation
The LPC mode uses a 5-signal communication interface
consisting of one control line, LFRAME#, which is driven by
the host to start or abort a bus cycle, and a 4-bit data bus,
LAD[3:0], which is used to communicate cycle type, cycle
direction, ID selection, address, data and sync fields. The
device enters standby mode when LFRAME# is high and
no internal operation is in progress.
The SST49LF004B supports both single-byte Firmware
Memory Read/Write cycles and single-byte LPC Memory
Read/Write cycles as defined in Intel’s Low-Pin-Count
Interface Specification, Revision 1.1. The host drives
LFRAME# low for one or more clock cycles to initiate an
LPC cycle. The last latched value of LAD[3:0] before
LFRAME# is the START value. The START value deter-
mines whether the SST49LF004B will respond to a Firm-
ware Memory Read/Write cycle or a LPC Memory Read/
Write cycle as defined in Table 3.
TABLE 3: F
See following sections for details of Firmware Memory and
LPC Memory cycle types. JEDEC standard SDP (Soft-
ware Data Protection) Program and Erase command
sequences are used to initiate Firmware and LPC Memory
Program and Erase operations. See Table 12 for a listing
of Program and Erase commands. Chip-Erase is only
available in PP mode.
START
Value
0000
1101
1110
Definition
Start of an LPC memory cycle. The direction
(Read or Write) is determined by the second field
of the LPC cycle.
Start of a Firmware Memory Read cycle
Start of a Firmware Memory Write cycle
START F
IRMWARE AND
IELD
D
LPC M
EFINITION
EMORY
S71232-02-000
C
Data Sheet
YCLES
T3.0 1232
12/03