mx27c1610 Macronix International Co., mx27c1610 Datasheet - Page 6

• Manufacturer Part Number: mx27c1610
• Description: 16m-bit [2m X 8/1m X 16] Cmos Otp Rom
• Manufacturer: Macronix International Co.

READ STATUS REGISTER
The MXIC's16 Mbit OTP ROM contains a status regis-
ter which may be read to determine when a program
operation is complete, and whether that operation com-
pleted successfully. The status register may be read at
any time by writing the Read Status command to the
CIR. After writing this command, all subsequent read
operations output data from the status register until an-
other valid command sequence is written to the CIR. A
Read Array command must be written to the CIR to re-
turn to the Read Array mode.
It should be noted that the contents of the status regis-
ter are latched on the falling edge of OE or CE which-
ever occurs last in the read cycle. This prevents pos-
sible bus errors which might occur if the contents of the
status register change while reading the status register.
CE or OE must be toggled with each subsequent status
read, or the completion of a program operation will not
be evident.
The Status Register is the interface between the micro-
processor and the Write State Machine (WSM). When
the WSM is active, this register will indicate the status
of the WSM, and will also hold the bits indicating whether
or not the WSM was successful in performing the de-
sired operation. The WSM can set status bit4 and bit7.
However, the WSM can only clear bit 7 but can not clear
bit 4. If Program fail status bit is detected, the Status
Register is not cleared until the "Clear Status Register
command" is issued. The MX27C1610 automatically out-
puts Status Register data when read after Page Pro-
gram or Read Status Command write cycle. The inter-
nal state machine is set for reading array data upon
device power-up.
P/N:PM0593
6
CLEAR STATUS REGISTER
The Program fail status bit (Q4) are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure
conditions(see Table below). By allowing the system
software to control the resetting of these bits, several
operations may be performed (such as cumulatively
programming several pages . The status register may
then be read to determine if an error occurred during
that programming series. This adds flexibility to the
way the device may be programmed. Additionally, once
the program fail bit happens, the program operation can
not be performed further. The program fail bit must be
reset by system software before further page program
are attempted. To clear the status register, the Clear
Status Register command is written to the CIR. Then,
any other command may be issued to the CIR. Note
again that before a read cycle can be initiated, a Read
command must be written to the CIR to specify whether
the read data is to come from the Array, Status Register
or Silicon ID.
MX27C1610
REV. 1.4, NOV. 19, 2002