74HCT32DR2G ON Semiconductor, 74HCT32DR2G Datasheet
74HCT32DR2G
Specifications of 74HCT32DR2G
Related parts for 74HCT32DR2G
74HCT32DR2G Summary of contents
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Quad 2−Input OR Gate with LSTTL−Compatible Inputs High−Performance Silicon−Gate CMOS The 74HCT32 is identical in pinout to the LS32. The device has TTL−compatible inputs. Features • Output Drive Capability: 10 LSTTL Loads • TTL/NMOS−Compatible Input Levels • Outputs Directly ...
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... FUNCTION TABLE Inputs ORDERING INFORMATION Device 74HCT32DR2G 74HCT32DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free GND A4 B4 Output Package SOIC−14 (Pb−Free) TSSOP− ...
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... SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter ...
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... I Maximum Input Leakage Current in I Maximum Quiescent Supply CC Current (per Package) DI Additional Quiescent Supply CC Current 1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 2. Total Supply Current = I + Σ CHARACTERISTICS (C = 50pF, Input t L Symbol Parameter ...
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INPUT 50 10% t PLH 90% OUTPUT Y 50% 10% t TLH Figure 1. Switching Waveforms OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure 2. Test Circuit A B ...
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... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...
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... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...