em78p134n ELAN Microelectronics Corp, em78p134n Datasheet - Page 12

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em78p134n

Manufacturer Part Number
em78p134n
Description
8-bit Microcontroller With Otp Rom
Manufacturer
ELAN Microelectronics Corp
Datasheet
EM78P134N
8-Bit Microcontroller with OTP ROM
6 •
Address
0A
0B
0C
0D
0E
00
01
02
03
04
05
06
07
08
09
0F
10
3F
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
"ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth
and tenth bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits
of the PC, and the ninth and tenth bits of the PC will remain unchanged.
Any instruction except “ADD R2,A” written to R2 (e.g. "MOV R2, A", "BC R2,
6",⋅etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain
unchanged.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for instructions
that would change the contents of R2. Such instructions will need one more
instruction cycle.
The Data Memory Configuration is as follows:
:
RC (Comparator Control Register II)
RD (System Control Register)
RE (Wake-up Control Register)
RF (Interrupt Status Register)
RB (Comparator Control Register I)
R7 ( TBLP:Table Point Register )
R8 ( TBHP:Table Point Register )
R9 (Unused)
RA (PWM Control Register)
Unused
R0
R1
R2
R3
R4
R6
R PAGE Registers
General Registers
(Status)
(Port 6)
(TCC)
(RSR)
(PC)
(-)
(This specification is subject to change without further notice)
Product Specification (V1.6) 06.02.2010
Unused
CONT
IOCC
IOCD
IOCB
IOCE
IOCF
IOC6
IOC7
IOC8
IOC9
IOCA
IOC PAGE Registers
(I/O Port Control Register)
(TMRH: PWM timer)
(TIMEL: PWM timer)
(PRDL: PWM period)
(DTL: Duty cycle of PWM)
(Control Register)
(Pull-down Register)
(Open-drain Register)
(Pull-high Register)
(WDT Control Register)
(Interrupt Mask Register)
(-)

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