em78p809n ELAN Microelectronics Corp, em78p809n Datasheet - Page 32

• Manufacturer Part Number: em78p809n
• Description: 8-bit Microcontroller
• Manufacturer: ELAN Microelectronics Corp

EM78P809N
8-Bit Microcontroller
28 •
Table 2. Mode Switching Control
Table 3. Operation Mode
In NORMAL mode, the CPU core and on-chip peripherals operate in oscillator
frequency.
In IDLE mode, the CPU core halts, but the on-chip peripheral and oscillator circuit
remain active. IDLE mode is released to NORMAL mode by any interrupt source. If the
ENI instruction is set, an interrupt will be serviced first followed by executing the next
instruction which is after the IDLE mode is released and the interrupt service is finished.
If the ENI instruction is not set, the next instruction will be executed which is after the
IDLE mode start instruction. IDLE mode can also be released by setting the /RESET
pin to low and executing a reset operation.
In SLEEP mode, the internal oscillator is turned off and all system operation is halted.
SLEEP mode is released by /SLEEP pin (level sensitive or edge sensitive can be set by
System Control Register (SCR) bit 0 (REM)).
instruction will be executed which is after the SLEEP mode start instruction. SLEEP
mode can also be released by setting the /RESET pin to low and executing a reset
operation. In level sensitive mode, the /SLEEP pin must be confirmed in low level
before entering SLEEP mode. In edge sensitive mode, SLEEP mode is started even
when the /SLEEP pin is in high level.
Table 4. Wake-up Methods
1. Individual interrupt source
2. WDT interrupt request
3. /INT0
4. ENI instruction is not
Signal
Clock
in IMR1, IMR2
executed
Operation Mode
Normal
Sleep
Normal
Idle
Wake-up Signal
Mode Switch
Normal
Normal
Normal
Sleep
Reset
Sleep
Idle
Idle
Set SIS = 1, execute SLEP instruction
/SLEEP pin wake up
Set SIS = 0, execute SLEP instruction
Interrupt
R5 (SIS) = 1+SLEP
SLEEP Mode
Frequency
Instruction
Turn on
Turn off
No effect
(This specification is subject to change without further notice)
(**)
Switch Method
Product Specification (V1.0) 07.26.2005
1. Wake-up
2. Jump to the next
After a warm-up period, the next
R5 (SIS)= 0 + SLEP
instruction or enter
IDLE mode
CPU Code
IDLE Mode
Instruction
Reset
Fosc
Halt
Peripherals
R5 (SIS)=(*)
On-chip
NORMAL
No effect
Reset
Note
Fosc
Halt
Mode
(**)