em78f644nso28s ELAN Microelectronics Corp, em78f644nso28s Datasheet - Page 78
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em78f644nso28s
Manufacturer Part Number
em78f644nso28s
Description
Flash Series 8-bit Microcontroller
Manufacturer
ELAN Microelectronics Corp
Datasheet
1.EM78F644NSO28S.pdf
(200 pages)
- Current page: 78 of 200
- Download datasheet (5Mb)
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
68 •
Bits 5~4 (SBIM1~SBIM0): Serial bus interface operation mode select
Bit 3 (UINVEN): Enable UART TX and RX port inverse output
Bits 2~0:
6.3.37 Bank0 R34: URS (UART Status Register)
Bit 7 (URRD8): UART receive data buffer 8
Bit 6 (EVEN):
Bit 5 (PRE):
Bit 4 (PRERR): Parity error flag. Set to “1” when parity error occurs and clear to “0”
Bit 3 (OVERR): Over running error flag. Set to “1” when overrun error occurs and
Bit 2 (FMERR): Framing error flag. Set to “1” when framing error occurs and clear to
Bit 1 (URBF):
Bit 0 (RXE):
URRD8
Bit 7
EVEN
Bit 6
UART read buffer full flag. Set to “1” when one character is received.
0: Disable TX and RX port inverse output
1: Enable TX and RX port inverse output
Not used, fixed to “0” all the time.
Select parity check
0: Odd parity
1: Even parity
Enable parity addition
0: Disable
1: Enable
by software.
clear to “0” by software.
“0” by software.
Reset to “0” automatically when read from URS register. URBF is
cleared by hardware when Receive is enabled. The URBF bit is
read-only. Therefore, read URS register is necessary to avoid
overrun error.
Enable Receive
0: Disable Receive
1: Enable Receive
SBIM1
Bit 5
PRE
0
0
1
1
PRERR
Bit 4
(This specification is subject to change without further notice)
SBIM0
OVERR
th
0
1
0
1
Bit 3
bit
Product Specification (V1.0) 05.05.2010
FMERR
Bit 2
Operation Mode
I/O mode
SPI mode
UART mode
I2C mode
URBF
Bit 1
Bit 0
RXE
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