MC14049UB
Hex Buffers
P−channel and N−channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic−level conversion using only one
supply voltage, V
V
Loads can be driven when the device is used as CMOS−to−TTL/DTL
converters (V
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
Features
1. Temperature Derating: All Packages: See Figure 4.
static voltages or electric fields referenced to the V
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high−impedance circuit. For proper operation, the ranges V
V
either V
MAXIMUM RATINGS
Symbol
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
in
DD
The MC14049UB hex inverter/buffer is constructed with MOS
This device contains circuitry to protect the inputs against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
High Source and Sink Currents
High−to−Low Level Converter
Supply Voltage Range = 3.0 V to 18 V
Meets JEDEC UB Specifications
V
Improved ESD Protection on All Inputs
Pb−Free Packages are Available*
V
V
Semiconductor Components Industries, LLC, 2004
T
I
V
P
v 18 V and V
T
T
I
out
DD
out
stg
in
IN
A
in
D
L
supply voltage for logic−level conversions. Two TTL/DTL
SS
can exceed V
or V
DC Supply Voltage Range
Input Voltage Range
Output Voltage Range
Input Current
Output Current
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
(DC or Transient)
(DC or Transient)
(DC or Transient) per Pin
(DC or Transient) per Pin
Plastic
SOIC
DD
DD
SS
). Unused outputs must be left open.
= 5.0 V, V
DD
v V
. The input−signal high level (V
DD
out
(Voltages Referenced to V
Parameter
v V
OL
DD
v 0.4 V, I
are recommended.
OL
SS
SS
3.2 mA). Note that pins
pin, only. Extra precautions
)
−0.5 to +18.0
−0.5 to +18.0
−55 to +125
−65 to +150
−0.5 to V
IH
Value
+0.5
+45
825
740
260
) can exceed the
10
DD
1
Unit
mW
mA
mA
SS
V
V
V
C
C
C
v
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
CASE 751B
SOEIAJ−16
CASE 948F
TSSOP−16
DT SUFFIX
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−16
SOIC−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
Publication Order Number:
16
16
16
1
1
1
MC14049UBCP
DIAGRAMS
MC14049UB
MARKING
MC14049UB/D
AWLYYWW
16
AWLYWW
1
14049U
ALYW
ALYW
049U
14