k9f2g08q0m Samsung Semiconductor, Inc., k9f2g08q0m Datasheet
k9f2g08q0m
Available stocks
Related parts for k9f2g08q0m
k9f2g08q0m Summary of contents
Page 1
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Document Title 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory Revision History Revision No History 0.0 1. Initial issue 0.1 1. Add the ,tf & Ibusy graph for 1.8V device (Page 34) 2. Add the data protection Vcc guidence for 1.8V device - below about 1 ...
Page 2
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Document Title 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory Revision History Revision No History 0.5 1. The value of AC parameters for K9F2G08U0M are changed. ITEM REH t REA t CEA t ADL 2. The definition and value of setup and hold time are changed. ...
Page 3
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory PRODUCT LIST Part Number K9F2G08Q0M-Y,P K9F2G16Q0M-Y,P K9F2G08U0M-Y,P K9F2G16U0M-Y,P FEATURES Voltage Supply -1.8V device(K9F2GXXQ0M): 1.70V~1.95V -3.3V device(K9F2GXXU0M): 2.7 V ~3.6 V Organization - Memory Cell Array -X8 device(K9F2G08X0M) : (256M + 8,192K)bit x 8bit -X16 device(K9F2G16X0M) : (128M + 4,096K)bit x 16bit ...
Page 4
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M PIN CONFIGURATION (TSOP1) K9F2GXXX0M-YCB0,PCB0/YIB0,PIB0 X16 X8 N.C N.C 1 N.C N.C 2 N.C N.C 3 N.C N.C 4 N.C N.C 5 N.C N.C 6 R/B R N.C N.C 10 N.C N.C 11 Vcc Vcc 12 Vss Vss 13 N.C N.C 14 N.C N.C 15 CLE CLE 16 ALE ALE N.C N.C 20 N.C N.C 21 N.C 22 N.C N.C N.C 23 N.C N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) ...
Page 5
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The (K9F2G08X0M) O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O ~ I/O I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper- ...
Page 6
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Figure 1-1. K9F2G08X0M (X8) Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE PRE Figure 2-1. K9F2G08X0M (X8) Array Organization 128K Pages ...
Page 7
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Figure 1-2. K9F2G16X0M (X16) Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE PRE Figure 2-2. K9F2G16X0M (X16) Array Organization ...
Page 8
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Product Introduction The K9F2GXXX0M is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8(X8 device) or 1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or 1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056- word(X16 device) cache register are serially connected to each other ...
Page 9
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F2GXXX0M-XCB0 Temperature Under Bias K9F2GXXX0M-XIB0 K9F2GXXX0M-XCB0 Storage Temperature K9F2GXXX0M-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins ...
Page 10
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M VALID BLOCK Parameter Symbol Valid Block Number NOTE : device 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre- sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits gram factory-marked bad blocks ...
Page 11
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M AC Timing Characteristics for Command / Address / Data Input Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time ALE to Data Loading Time NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ...
Page 12
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
Page 13
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
Page 14
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
Page 15
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M NAND Flash Technical Notes Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig- nificant bit) pages of the block. Random page address programming is prohibited. ...
Page 16
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system design gets more flexible ...
Page 17
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M NOTE I/O Device I/Ox K9F2G08X0M(X8) I I/O 7 K9F2G16X0M(X16) I I/O 15 Command Latch Cycle CLE CE WE ALE I/Ox K9F2G16X0M : I must be set to "0" Address Latch Cycle t CLS CLE ALS ALE t DS I/Ox Col. Add1 K9F2G16X0M : I must be set to "0" ...
Page 18
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Input Data Latch Cycle CLE ALE t ALS I/Ox DIN 0 Serial Access Cycle after Read t CEA CE t REA I/ R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ...
Page 19
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Serial Access Cycle after Read t CEA CE t REA I/ R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Serial Access Cycle after Read t CEA CE t REA I/ R/B NOTES : Transition is measured 200mV from steady state voltage with load ...
Page 20
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Status Read Cycle CLE I/Ox K9F2G16X0M : I must be set to "0" t CLR t CLS t CLH CEA t WHR IR* 70h 20 Preliminary FLASH MEMORY t CHZ RHZ* REA t OH Status Output ...
Page 21
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Read Operation CLE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox Col. Add2 00h Col. Add1 Column Address R 30h Row Add1 Row Add2 Row Add3 ...
Page 22
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M FLASH MEMORY 22 Preliminary ...
Page 23
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Page Program Operation CLE ALE RE I/Ox 80h Co.l Add1 Col. Add2 Row Add1 SerialData Column Address Input Command R/B NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ...
Page 24
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M FLASH MEMORY 24 Preliminary ...
Page 25
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M FLASH MEMORY 25 Preliminary ...
Page 26
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M FLASH MEMORY 26 Preliminary ...
Page 27
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 Row Address R/B Auto Block Erase Setup Command t t BERS WB D0h Busy Erase Command 27 Preliminary FLASH MEMORY 70h I/O 0 I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase ...
Page 28
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle K9F2G08Q0M K9F2G08U0M K9F2G16Q0M K9F2G16U0M ID Definition Table Access command = 90H Description 1 st Byte Maker Code 2 nd Byte Device Code 3 rd Byte Don’t care 4 th Byte Page Size, Block Size, Spare Size, Organization ...
Page 29
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M 4th ID Data Description 1KB Page Size 2KB (w/o redundant area ) Reserved Reserved 64KB Block Size 128KB (w/o redundant area ) 256KB Reserved Redundant Area Size 8 ( byte/512byte Organization x16 50ns / 30ns 25ns Serial AccessMinimum Reserved Reserved FLASH MEMORY I/O7 I/O6 I/O5 I/O4 I/ ...
Page 30
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Device Operation PAGE READ Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h-30h to the command register along with five address cycles. In two consecutive read operations, the second one doesn’t need 00h command, which five address cycles and 30h command initiates that operation ...
Page 31
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 5Cycles Col Add1,2 & Row Add1,2,3 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112(X8 device) or words up to 1056(X16 device single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte, X16 device:1time/8word) ...
Page 32
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Figure 9. Random Data Input In a Page R/B I/Ox 80h Address & Data Input Col Add1,2 & Row Add1,2,3 Data Cache Program Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis- ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell ...
Page 33
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after com- pletion of the previous cycle, which can be expressed as the following formula ...
Page 34
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address (X8 Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
Page 35
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 50h respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence. ...
Page 36
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto- page read function. Auto-page read function is enabled only when PRE pin is tied to V without latency ...
Page 37
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
Page 38
... K9F2G08Q0M K9F2G16Q0M K9F2G08U0M K9F2G16U0M Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum required before internal cir- IL cuit gets ready for any command sequences as shown in Figure 18 ...