ml6696 Microsemi Corporation, ml6696 Datasheet - Page 4
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ml6696
Manufacturer Part Number
ml6696
Description
100base-x Fiber Physical Layer
Manufacturer
Microsemi Corporation
Datasheet
1.ML6696.pdf
(16 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
ml6696CH
Manufacturer:
MICROLINEAR
Quantity:
20 000
ML6696
PIN DESCRIPTION
PIN
30 (32) CAPB
31, 32
(33)
33 (34) V
34 (35) V
35, 36
(36, 37) AV
37 (38) LINK100
38 (39) AGND4A
39 (40) AV
40 (41) AV
41 (42) AV
42 (43) RTSET
43, 44
(44)
45, 46
(45)
4
NAME
AGND4B
AGND3
IOUT
IN–
IN+
CC
CC
CC
CC
4B
4A
3B
3A
FUNCTION
Data quantizer input bias bypass
capacitor input. The capacitor tied
between this pin and AV
the quantizer’s internal input bias
reference. A 0.1µF surface-mount
capacitor is recommended.
Analog ground
Receive quantizer negative input.
This input should be tied to
AV
capacitor. (0.01µF recommended)
Receive quantizer positive input.
This input receives 100BASE-FX
signals from the network optical
receiver through an AC coupling
capacitor. (0.01µF recommended).
Analog positive power supply
100BASE-FX link activity open-
drain output. LINK100 pulls low
when there is 100BASE-FX activity
at VIN+/–. This output is capable
of sinking sufficient current to
directly drive a status LED in
series with a current limiting
resistor.
Analog ground
Analog positive power supply
Analog positive power supply
Analog positive power supply
Transmit level bias resistor. For
100BASE-FX, an external 2.32k ,
1% resistor connected between
RTSET and AGND3 sets a
precision constant bias current
that gives a nominal output "on"
current of 75mA at I
Analog ground
Transmit LED output. This pin
connects through an external 15
resistor to AV
used to drive a network LED.
CC
(Pin Number in Parentheses is for PLCC Version) (Continued)
Q through an AC coupling
CC
when the part is
OUT
.
CC
filters
PIN
47, 48
(46)
49, 50,
51 (47) AGND2
52 (48) AV
53 (49) EDOUT
54 (50) ECLK
55 (51) EDIN
56 (52) AV
57 (1)
58 (2)
59 (3)
NAME
IOUT
CLKREF
AGND1
TXD3
CC
CC
2
1
FUNCTION
Initialization Interface clock
Transmit clock TTL input. This
Transmit data TTL input. TXD<3:0>
Transmit LED output. This open-
collector current output drives
NRZI waveforms into a network
LED.
Analog ground
Analog positive power supply
Initialization Interface data out
CMOS input. With EDIN low at
power up, EDOUT has no
function. With EDIN floating at
power up, EDOUT is the serial
data input for configuration data
from an EEPROM. With EDIN high
at power up, EDOUT is the input
for configuration data from an
external microcontroller. (Table 1)
CMOS input/output. With EDIN
low at power up, ECLK is inactive.
With EDIN floating at power up,
ECLK is the ML6696’s clock
output for timing the configuration
data from an external EEPROM.
With EDIN high at power up,
ECLK is the clock input for timing
configuration data from an
external microcontroller. (Table 1)
Initialization Interface mode
select and EEPROM interface data
in CMOS input/output. EDIN
selects one of three possible
interface modes at power up. See
the Initialization Interface section
for more information. (Table 1)
Analog positive power supply
25MHz clock is the frequency
reference for the internal TX PLL
clock synthesizer and logic. This
pin should be driven by an
external 25MHz clock at TTL
levels.
Analog ground
inputs accept TX data symbols from
the MII. Data appearing at TXD<3:0>
are clocked into the ML6696 on the
rising edge of TXCLK.