ST16C2550CQ48 EXAR [Exar Corporation], ST16C2550CQ48 Datasheet - Page 19

• Manufacturer Part Number: ST16C2550CQ48
• Description: 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

xr
REV. 4.4.0
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
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•
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•
•
•
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•
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ISR[0]: Interrupt Status
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•
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
ISR[5:4]: Reserved
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.4
4.4.1
4.4.2
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default).
P
RIORITY
Interrupt Status Register (ISR) - Read-Only
1
2
3
4
5
-
Interrupt Generation:
Interrupt Clearing:
L
EVEL
Table
8, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
B
IT
0
1
0
0
0
0
-3
ISR R
T
B
ABLE
EGISTER
IT
1
1
1
0
0
0
-2
8: I
S
B
NTERRUPT
TATUS
IT
1
0
0
1
0
0
-1
B
ITS
B
IT
S
0
0
0
0
0
1
-0
OURCE AND
19
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
None (default)
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
P
RIORITY
S
L
OURCE OF INTERRUPT
EVEL
Table
8).
ST16C2550