ST16C654CJ68 EXAR [Exar Corporation], ST16C654CJ68 Datasheet - Page 6

• Manufacturer Part Number: ST16C654CJ68
• Description: QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER
• Manufacturer: EXAR [Exar Corporation]

ST16C654/654D
SYMBOL DESCRIPTION
-CS A-B
-CS C-D
-CSRDY
D0-D2
D3-D7
GND
GND
INT A-B
INT C-D
Symbol
Rev. 4.10
66-68
15,21
16,20
50,54
40,57
49,55
6,23
1-5
68
-
13,17
64,68
88-90
91-95
96,20
46,71
12,18
63,69
Pin
100
76
53-55
38,42
56-60
14,28
45,61
37,43
7,11
6,12
64
-
Signal
type
Pwr
I/O
O
I
I
UARTs (A-D) are enabled when the -CS pin is a logic 0. An
individual UART channel is selected by the data contents of
address bits A3-A4. When the 16 mode is selected (68/100
pin devices), this pin functions as -CSA, see definition under
-CS A-B. This pin is not available on 64 pin packages which
operate in the 16 mode only.
associated with the 16 mode only, and for individual chan-
nels, “A” through “D.” When in 16 Mode, these pins enable
data transfers between the user CPU and the ST16C654 for
the channel(s) addressed. Individual UART sections (A, B,
C, D) are addressed by providing a logic 0 on the respective
-CS A-D pin. When the 68 mode is selected, the functions
of these pins are reassigned. 68 mode functions are de-
scribed under the their respective name/pin headings.
Control Status Ready (active low) - This feature is available
on 100 pin QFP packages only. On 100 pin packages, the
Contents of the FIFORDY Register is read when this pin is
a logic 0. However it should be noted, D0-D3 will contain the
inverted logic states of TXRDY, status bits A-D, and D4-D7
the inverted logic states of RXRDY, status bits D4-D7.
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Signal and power ground.
with the 16 mode only. These pins provide individual
channel interrupts, INT A-D. INT A-D are enabled when
MCR bit-3 is set to a logic 1, interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
Chip Select A, B, C, D (active low) - This function is
Data Bus (Bi-directional) - These pins are the eight bit, three
Interrupt A, B, C, D (active high) - This function is associated
5-70
Pin Description