thc63lvd1023b THine Electronics,Inc., thc63lvd1023b Datasheet
thc63lvd1023b
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... THC63LVD1023B_Rev1.20_E 135MHz 67Bits LVDS Transmitter General Description The THC63LVD1023B transmitter is designed to sup- port Single Link transmission between Host and Flat Panel Display and Dual Link transmission between Host and Flat Panel Display up to 1080p/QXGA resolu- tions. The THC63LVD1023B converts 67bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream ...
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... THC63LVD1023B _Rev1.20_E Pin Out (top view) N/C 109 B17/TD16 110 B18/TE10 111 B19/TE11 112 VCC 113 GND 114 R20/TE12 115 R21/TE13 116 R22/TE14 117 R23/TE15 118 R24/TE16 119 R25/TA20 120 R26/TA21 121 R27/TA22 122 R28/TA23 123 R29/TA24 124 VCC 125 GND 126 ...
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... THC63LVD1023B _Rev1.20_E Pin Description Pin Name ASYNC=L ASYNC=H TA1+, TA1- TB1+, TB1- TC1+, TC1- TD1+, TD1- TE1+, TE1- TCLK1+, TCLK1- TA2+, TA2- TB2+, TB2- TC2+, TC2- TD2+, TD2- TE2+, TE2- TCLK2+, TCLK2- TB12~TB1 R19 ~ R10 0,TA16~TA 10 TC15~TC1 G19 ~ G10 0,TB16~TB 13 TE11~TE10 ...
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... THC63LVD1023B _Rev1.20_E Pin Description (Continued) Pin Name ASYNC=L ASYNC=H *1 CONT11 , TE23,TE24 *1 CONT12 *1 CONT21 , TE25,TE26 *1 CONT22 DE1,DE2 TD26,TE22 VSYNC1, TD25,TE21 VSYNC2 HSYNC1, TD24,TE20 HSYNC2 CLKIN1 CLKIN2 R/F RS MAP (See Fig7 to 9 and Table4 to10) MODE1, MODE0 *1 : CONT## are DATA pins that user can use as data like RGBdata. ...
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... THC63LVD1023B _Rev1.20_E Pin Name ASYNC=L ASYNC=H MODE2 (See Fig.5) MODE3 ASYNC /PDWN *2 PRBS Reserved N/C 29, 33, 109 3, 13, 82, 93, VCC 4, 14, 83, 94, GND 43, 49, 55, LVCC 37, 42, 48, LGND 54, 60, 66, 72 PVCC PGND 34, 36, 73 Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of ...
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... THC63LVD1023B _Rev1.20_E Absolute Maximum Ratings Supply Voltage ( CMOS/TTL Input Voltage LVDS Driver Output Voltage Output Current Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4sec) Maximum Power Dissipation Recommended Operating Conditions All Supply Voltage Operating Ambient Temperature MODE<1:0>=LL Dual-in/Dual-out MODE< ...
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... THC63LVD1023B_Rev1.20_E Electrical Characteristics CMOS/TTL DC Specifications Symbol Parameter a High Level Data Input Voltage Low Level Data Input Voltage IL c High Level Control Input Voltage V IHC c Low Level Control Input Voltage V ILC d High Level Control Input Voltage V IHM d Middle Level Control Input Voltage ...
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... THC63LVD1023B _Rev1.20_E Electrical Characteristics (Continued) Supply Current Symbol Parameter Transmitter Supply Current I TCCW (Worst Case Pattern) Fig1. Transmitter Power Down Supply I TCCS Current TCLK1+ Txy+ x=A,B,C,D,E y=1,2 Fig1. Test Pattern (LVDS Output Full Toggle Pattern) Copyright©2008 THine Electronics, Inc. Condition MODE<1:0>=HH Single-in/Single-out ...
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... THC63LVD1023B_Rev1.20_E Switching Characteristics Symbol Parameter t CLK IN Period(Fig4,5) TCIP t CLK IN High Time(Fig4,5) TCH t CLK IN Low Time(Fig4,5) TCL t TTL Data Setup to CLK IN(Fig4, TTL Data Hold from CKL IN(Fig4,5) TH CLK IN to TCLK+/- Delay(Fig4,5) t MODE<1:0>=LL TCD Dual-in/Dual-out t CLK OUT Period(Fig6) TCOP t LVDS Transition Time(Fig2) ...
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... THC63LVD1023B _Rev1.20_E AC Timing Diagrams V =(TA+)-(TA-) diff TA+ 5pF 100Ω TA- LVDS Output Load Fig2. LVDS Output Load and Transition Time CLKINx x=1,2 /PDWN TCLKx+/- x=1,2 t DEINT t TCIP CLKIN DE t DEH Note : In single-in/dual-out, DDR off mode (MODE<2:0>=LHL), the period between rising edges should always satisfy following equations ...
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... THC63LVD1023B_Rev1.20_E AC Timing Diagrams (Continued) t TCH CLKINx V V REF REF x=1,2 t Rxn,Gxn,Bxn TS HSYNCx VSYNCx V Current Data DEx REF CONTx1 CONTx2 x=1,2 n=0-9 TCLKx+/- x=1,2 Txy+/- x=1,2 y=A,B,C,D,E Note: CLKINx : for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line. x=1,2 Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing t TCH CLKINx ...
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... THC63LVD1023B_Rev1.20_E AC Timing Diagrams (Continued) Tyx+/- Tyx6 Tyx5 Tyx4 TCLKx 1 A,B,C,D,E Copyright©2008 THine Electronics, Inc. t TOP2 t TOP3 t TOP4 t TOP5 t TOP6 t TOP0 t TOP1 Tyx3 Tyx2 Tyx1 Tyx0 Tyx6 diff t TCOP Note (Tyx+) - (Tyx-) , (TCLKx+) - (TCLKx-) diff Fig6. LVDS Output Data Position ...
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... THC63LVD1023B_Rev1.20_E Input Data Mapping X X=R X=G X=B Y= None • Table2. TTL/CMOS Input Data Mapping (Single-in mode, MODE1=H 30-bit Copyright©2008 THine Electronics, Inc. • Table1. Input Color Data naming rule ...
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... THC63LVD1023B_Rev1.20_E Input Data Mapping (Continued) • Table3. TTL/CMOS Input Data Mapping (Dual-in mode, MODE1=L Data Signals 30-bit 24-bit 18-bit 30-bit RE0 R10 RE1 R11 RE2 RE0 R12 RE3 RE1 R13 RE4 RE2 RE0 R14 RE5 RE3 RE1 R15 RE6 RE4 RE2 ...
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... THC63LVD1023B_Rev1.20_E LVDS Output Data Mapping Previous Cycle (2nd Pixel Data) TCLK1+ Tx1+/- Tx11(n-1) Tx10(n-1) x=A,B,C,D,E Previous Cycle TCLK1+ Tx1+/- Tx11(n-1) Tx10(n-1) x=A,B,C,D,E Tx2+/- Tx21(n-1) Tx20(n-1) x=A,B,C,D,E Copyright©2008 THine Electronics, Inc. Current Cycle (1st Pixel Data) Tx16(n) Tx15(n) Tx14(n) Tx13(n) Fig7. TTL Data Inputs Mapped to LVDS outputs ...
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... THC63LVD1023B_Rev1.20_E LVDS Output Data Mapping (Continued) • Table4. LVDS Output Data Mapping ( LVDS Output Data TA10 TA11 TA12 TA13 TA14 TA15 TA16 TB10 TB11 TB12 TB13 TB14 TB15 TB16 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TD10 TD11 TD12 TD13 TD14 ...
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... THC63LVD1023B_Rev1.20_E LVDS Output Data Mapping (Continued) • Table5. LVDS Output Data Mapping ( Mapping Mode(Input Pin Name) LVDS Mode2 Output Data Mode1 (1st Link) MAP= MAP= V IHM TA10 R14 TA11 R15 TA12 R16 TA13 R17 TA14 R18 TA15 R19 TA16 G14 TB10 ...
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... THC63LVD1023B_Rev1.20_E LVDS Output Data Mapping (Continued) Single-in/Dual-out, DDR On or Off ( Mapping Mode(Input Pin Name) LVDS Mode2 Output Data Mode1 (1st Link) MAP= MAP= V IHM TA10 R14 TA11 R15 TA12 R16 TA13 R17 TA14 R18 TA15 R19 TA16 G14 TB10 G15 ...
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... THC63LVD1023B _Rev1.20_E LVDS Output Data Mapping (Continued) Single-in/Dual-out, DDR On or Off ( Mapping Mode(Input Pin Name) LVDS Output Data Mode1 (1st Link) MAP= MAP= V IHM TA10 R24 TA11 R25 TA12 R26 TA13 R27 TA14 R28 TA15 R29 TA16 G24 TB10 G25 ...
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... THC63LVD1023B_Rev1.20_E LVDS Output Data Mapping (Continued) • Table7. LVDS Output Data Mapping ( Mapping Mode(Input Pin Name) LVDS Output Data Mode1 Mode2 (1st Pixel) MAP= MAP= V IHM TA10(n) R14 TA11(n) R15 TA12(n) R16 TA13(n) R17 TA14(n) R18 TA15(n) R19 TA16(n) G14 TB10(n) ...
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... THC63LVD1023B_Rev1.20_E LVDS Output Data Mapping (Continued) • Table8. LVDS Output Data Mapping ( Mapping Mode(Input Pin Name) LVDS Mode2 Output Data Mode1 (1st Link) MAP= MAP= V IHM TA10 R14 TA11 R15 TA12 R16 TA13 R17 TA14 R18 TA15 R19 TA16 G14 TB10 ...
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... THC63LVD1023B _Rev1.20_E LVDS Output Data Mapping (Continued) • Table9. LVDS Output Data Mapping ( LVDS Mapping(MAP=Don’t care) Output Data (1st Link) TA10 TA11 TA12 TA13 TA14 TA15 TA16 TB10 TB11 TB12 TB13 TB14 TB15 TB16 TC10 TC11 TC12 TC13 TC14 TC15 ...
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... THC63LVD1023B _Rev1.20_E LVDS Output Data Mapping (Continued) • Table10. LVDS Output Data Mapping ( LVDS Mapping(MAP=Don’t care) Output Data (1st Link) TA10 TA11 TA12 TA13 TA14 TA15 TA16 TB10 TB11 TB12 TB13 TB14 TB15 TB16 TC10 TC11 TC12 TC13 TC14 TC15 ...
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... Don't connect and disconnect the LVDS cable , when the power is supplied to the system. 2)GND Connection Connect the each GND of the PCB which THC63LVD1023B and LVDS- better for EMI reduction to place GND cable as close to LVDS cable as possible. 3)Multi Drop Connection Multi drop connection is not recommended ...
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... THC63LVD1023B _Rev1.20_E Package 108 109 144 1 1.25TYP 0.17 ± 0.05 Copyright©2008 THine Electronics, Inc. TOP VIEW 73 INDEX MARK MIRROR FINISH 36 0.50 0.22 ± 0.05 25/ 0.10 M 1.70MAX 1.40 ± 0.05 Unit : mm THine Electronics, Inc. ...
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... THC63LVD1023B _Rev1.20_E Notices and Requests 1.)The product specifications described in this material are subject to change without prior notice. 2.)The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material ...