SC220 ZARLINK [Zarlink Semiconductor Inc], SC220 Datasheet - Page 19

• Manufacturer Part Number: SC220
• Description: XpressFlow 2020 Ethernet Routing Switch Chipset
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

XpressFlow-2020 Series –
Ethernet Switch Chipset
2.3.5 Register Map
© 1998 Vertex Networks, Inc.
1999
Note: All 32-bit registers are D-word aligned.
Register Description
Device Configuration Registers (DCR)
Interrupt Controls
Buffer Memory Interface
Buffers & Stacks Management
GCR
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
ISR
ISRM
IMSK
IAR
MWAR
MRAR
MBAR
MWBS
MRBS
MWDR
MWDX
MRDR
MRDX
FCBBA Frame Control Buffer – Base Address
FCBA
FCBR
FCBAG Frame Control Buffer – Buffer Aging Status
FCBSA Frame Ctrl Buffer Stack – Base Address
FCBSL
FCBST
FCBSS Frame Ctrl Buffer Stack – Allocation Status
Frame Control Buffers
All 16-bit registers are also D-word aligned and right justified.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a
These registers are reserved for system diagnostic usage only.
P
Global Control Register
Device Status Register
Signature & Revision Register
ID Register
Local Control Register
Interface Status Register
Bus Credit Register
Interrupt Status Register – Unmasked
Interrupt Status Register – Masked
Interrupt Mask Register
Interrupt Acknowledgment Register
Memory Write Address Register – Single Cycle
Memory Read Address Register – Single Cycle
Memory Address Register – Burst Mode
Memory Write Burst Size (in D-words)
Memory Read Burst Size (in D-words)
Memory Write Data Register
Memory Write Data Register – Byte Swapping
Memory Read Data Register
Memory Read Data Register – Byte Swapping
Frame Control Buffer – Buffer Allocation
Frame Control Buffer – Buffer Release
Frame Ctrl Buffer Stack – Size Limit
Frame Ctrl Buffer Stack – Buffer Low Threshold hDA0
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
single operation.
R
E
L
I
M
I
N
A
R
Y
I
18
N
F
O
Endian
hFA0
hFB0
hE6C
hE6C
hD00
hD20
hD20
hD30
hD80
hD90
hDB0
hF00
hF00
hF10
hF20
hF30
hF40
hF50
hF80
hF90
hE08
hE18
hE28
hE40
hE50
hE68
hE68
Little
R
I/O Offset
M
Endian
hE6C
hE6C
hDA2
hDB2
A
hFA2
hFB2
hE08
hE18
hE28
hE42
hE52
hE68
hE68
hD02
hD22
hD22
hD32
hD82
hD92
hF02
hF02
hF12
hF22
hF32
hF42
hF52
hF82
hF92
Big
T
I
XpressFlow Engine
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
32-bit
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Size
Reg.
O
N
Rev. 4.5 – February
W/R
W/--
W/R
W/R
W/R
W/R
W/--
W/R
W/R
W/R
W/R
W/R
W/--
W/--
W/R
W/--
W/R
W/R
W/R
--/R
--/R
--/R
--/R
--/R
--/R
--/R
--/R
--/R
--/R
SC220
Note: