TC1270 MICROCHIP [Microchip Technology], TC1270 Datasheet - Page 5

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TC1270

Manufacturer Part Number
TC1270
Description
4-Pin ?P Reset Monitors
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet

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3.0
3.1
The TC1270/TC1271 provides accurate V
ing and reset timing during power-up, power-down, and
brownout/sag conditions, and rejects negative-going
transients (glitches) on the power supply line. Figure
3-1 shows the maximum transient duration vs.
maximum negative excursion (overdrive) for glitch
rejection. Any combination of duration and overdrive
that lays under the curve will not generate a reset
signal. Combinations above the curve are detected as
a brownout or power-down. Transient immunity can be
improved by adding a capacitor in close proximity to the
V
FIGURE 3-1:
3.2
The TC1270 RESET output is valid to V
Below this voltage the output becomes an "open
circuit" and does not sink current. This means CMOS
logic inputs to the µP will be floating at an
undetermined voltage. Most digital systems are
completely shut down well above this voltage.
However, in situations where RESET must be
maintained valid to V
©
CC
2002 Microchip Technology Inc.
pin of the TC1270/TC1271.
400
320
240
160
80
APPLICATIONS INFORMATION
V
RESET Signal Integrity During
Power-Down
0
CC
1
V
CC
T
TC127xR/S/T
RESET COMPARATOR OVERDRIVE,
Transient Rejection
A
CC
°C
MAXIMUM TRANSIENT
DURATION VS.
OVERDRIVE FOR GLITCH
REJECTION AT 25°C
10
V
= 0V, a pull-down resistor must
TC127LMJ
TH
Duration
- V
CC
(mV)
100
Overdrive
V
TH
CC
CC
monitor-
1000
= 1.0V.
be connected from RESET to ground to discharge stray
capacitances and hold the output low (Figure 3-2). This
resistor value, though not critical, should be chosen
such that it does not appreciably load RESET under
normal operation (100kΩ will be suitable for most
applications). Similarly, a pull-up resistor to V
required for the TC1271 to ensure a valid high RESET
for V
FIGURE 3-2:
3.3
Some µP's (such as Motorola 68HC11) have bi-
directional reset pins. Depending on the current drive
capability of the processor pin, an indeterminate logic
level may result if there is a logic conflict. This can be
avoided by adding a 4.7 kΩ resistor in series with the
output of the TC1270/TC1271 (Figure 3-3). If there are
other components in the system which require a reset
signal, they should be buffered so as not to load the
reset line. If the other components are required to
follow the reset I/O of the µP, the buffer should be
connected as shown with the solid line.
FIGURE 3-3:
V
CC
CC
TC1270
V
GND
below 1.1V.
CC
Processors With Bidirectional
I/O Pins
RESET
TC1270/TC1271
TC1270
4.7k
V
GND
V
CC
ENSURING RESET VALID
TO V
INTERFACING TO
BIDIRECTIONAL
RESET I/O
CC
RESET
RESET
CC
Buffer
= 0V
V
GND
µP
CC
100k
R1
DS21381B-page 5
Buffered RESET
To Other System
Components
CC
is

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