s3c72c8 Samsung Semiconductor, Inc., s3c72c8 Datasheet
s3c72c8
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s3c72c8 Summary of contents
Page 1
... S3C72C8 offers an excellent design solution for a low CDP and a card reader pins of the 44-pin QFP pins of the 42-pin SDIP package can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C72C8's advanced CMOS technology provides for low power consumption. ...
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... CPU clock divider circuit ( 64) Instruction Execution Times • 0.67, 1.33, 10.7 µ MHz (main) • 0.95, 1.91, 15.3 µs at 4.19 MHz (main) • 122 µs at 32.768 kHz (subsystem) Operating Temperature • – Operating Voltage Range • 1 5.5 V Package Type • 44-pin QFP, 42-pin SDIP S3C72C8/P72C8 ...
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... IN OUT Interrupt Control Clock Block Internal Interrupts Instruction Decoder Arithmetic and Logic Unit 512 x 4-Bit Data Memory Figure 1-1. S3C72C8 Simplified Block Diagram PRODUCT OVERVIEW Watch Dog Timer Basic Timer Watch Timer Instruction Register LCD Driver/ Controller Program Counter SIO Program Status Word ...
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... PRODUCT OVERVIEW PIN ASSIGNMENTS P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3 X TEST XT Figure 1-2. S3C72C8 44-QFP Pin Assignment Diagram 1 S3C72C8 (44-QFP-1010B) 7 OUT OUT S3C72C8/P72C8 COM5/SEG14 33 COM6/SEG13 32 COM7/SEG12 31 SEG11/P7.3 30 SEG10/P7.2 29 SEG9/P7.1 28 SEG8/P7.0 27 SEG7/P6.3 26 SEG6/P6.2 25 SEG5/P6.1 24 SEG4/P6.0 23 ...
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... S3C72C8/P72C8 P1.0/TCLO1/INT0 P1.1/TCL1/INT1 P1.2/CLO/INT2 P1.3/BUZ/INT4 P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3 RESET P0.3/BTCO P0.2/SI P0.1/SO Figure 1-3. S3C72C8 42-SDIP Pin Assignment Diagram COM1 1 COM0 OUT TEST OUT PRODUCT OVERVIEW COM2 42 COM3 41 COM4/SEG15 ...
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... Individual pins are software configurable as open-drain or push-pull output; 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. P6.0-P6.3 I/O Same as port5 P7.0-P7.3 I/O Same as port5 1-6 Table 1-1. S3C72C8 Pin Descriptions Description S3C72C8/P72C8 Circuit Number Share Pin Type SCK E–1 16 (22) 15 (21) SO ...
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... S3C72C8/P72C8 Table 1-1. S3C72C8 Pin Descriptions (Continued) Pin Name Pin Type SEG0-SEG3 I/O LCD segment display signal output pins SEG4-SEG7 SEG8-SEG11 SEG12-SEG15 O LCD segment display output pins COM0-COM3 O LCD common signal output pins COM4-COM7 I/O LCD common signal output pins SCK I/O Serial interface clock signal ...
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... PRODUCT OVERVIEW Table 1-1. S3C72C8 Pin Descriptions (Continued) Pin Name Pin Type INT2 I Quasi-interrupt with detection of rising or falling edges. INT4 I External interrupt with detection of rising or falling edges. INTP30 I Key scan interrupts inputs. INTP31 TEST I System test pin V – Power supply pin DD V – ...
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... S3C72C8/P72C8 PIN CIRCUIT DIAGRAMS Pull-Up Resistor Enable PNE Data Output DIsable V DD Pull-Up Resistor In Schmitt Trigger Input Figure 1-4. Pin Circuit Type B Pull-up Resistor V DD Figure 1-5. Pin Circuit Type E-1 PRODUCT OVERVIEW V DD P-CH I/O 1-9 ...
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... PRODUCT OVERVIEW Pull-Up Resistor Enable PNE Ouput Disable Data 1-10 PNE Data Figure 1-6. Pin Circuit Type E-2 Pull-Up Resistor Circuit Type E-4 Figure 1-7. Pin Circuit Type E Out V DD P-CH I/O LCON.1 S3C72C8/P72C8 ...
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... S3C72C8/P72C8 COM Data V LC4 V SS PNE Data Figure 1-8. Pin Circuit Type E-4 LC1 Figure 1-9. Pin Circuit Type H-4 PRODUCT OVERVIEW V DD Out Out LPOT.3 1-11 ...
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... PRODUCT OVERVIEW SEG/COM Data 1-12 LC1 V LC2 V LC3 LC4 Figure 1-10. Pin Circuit Type H-6 S3C72C8/P72C8 Out LPOT.3 ...
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... S3C72C8/P72C8 LC2 SEG Data Output Disable V LC3 V SS Figure 1-11. Pin Circuit Type H-7 PRODUCT OVERVIEW Out 1-13 ...
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... PRODUCT OVERVIEW 1-14 Pull-Up Resistor Enable Circuit SEG Type H-7 Output DIsable Circuit Data Type E-4 PNE Figure 1-12. Pin Circuit Type H-13 S3C72C8/P72C8 V DD P-CH ...
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... S3C72C8/P72C8 (Digital) (Analog) Pull-Up Resistor Enable Data Output DIsable INTK External REF (P2.3 only) Comparator Digital or Analog can be seleted by software. Figure 1-13. Pin Circuit Type F-8 PRODUCT OVERVIEW V DD Pull-up Resistor P- I REF 1-15 ...
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... S3C72C8/P72C8 15 ELECTRICAL DATA OVERVIEW In this section, information on S3C72C8 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics — Subsystem clock oscillator characteristics — ...
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... V + 0.3 DD – 0 0.3 DD – 15 – (Peak value 100 (Peak value – – 150 Duty . Min Typ Max 0.8 V – – 0 – – 0 0.1 V – 1.0 – – DD – – 2.0 0.4 S3C72C8/P72C8 Units Units ...
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... S3C72C8/P72C8 Table 15-2. D.C. Electrical Characteristics (Continued – Parameter Symbol Input High I V LIH1 I Leakage All input pins except those Current specified below for LIH2 Input Low I V LIL1 I Leakage All input pins except RESET, X Current X out ...
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... V 10% 6.0 MHz ± 4.19 MHz = 3 V ± 10% 6.0 MHz 4.19 MHz 6.0 MHz = 5 V 10% 4.19 MHz ± ± 10% 6.0 MHz 4.19 MHz = 3 V ± 10 ± 10% DD SCMOD = = 5 V ± 10% 0000B ± 10 ± 10% SCMOD = 0100B = 3 V ± 10% S3C72C8/P72C8 Min Typ Max – 3.0 8.0 2.3 5.5 1.5 4.0 1.0 3.0 1.3 2.5 1.2 1.8 0.5 1.5 0.44 1.0 – 15.0 30 5.0 15 2.5 5 0.5 3 ...
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... S3C72C8/P72C8 Table 15-3. Main System Clock Oscillator Characteristics (T = – 1 5 Oscillator Clock Configuration Ceramic Xin Xout Oscillator C1 C2 Crystal Xin Xout Oscillator C1 C2 External Xin Xout Clock RC Xin Xout Oscillator R NOTES: 1. Oscillation frequency and Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated ...
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... Oscillator Voltage Range (V) C2 MIN MAX 33 2.0 5.5 (2) 2.0 5.5 (3) 2.0 5.5 Min Typ – 32 32.768 – 1.0 – – – 32 – – 5 – S3C72C8/P72C8 Remarks Leaded Type On-chip C Leaded Type On-chip C SMD Type Max Units 35 kHz 100 kHz 15 µs ...
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... S3C72C8/P72C8 ( Parameter Input Capacitance Output Capacitance I/O Capacitance Table 15-7. Comparator Electrical Characteristics (T = – 4 5 Parameter Input Voltage Range Reference Voltage Range Internal Input Voltage Accuracy External Input Leakage Current Table 15-6. Input/Output Capacitance Symbol Condition MHz ...
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... 5.5 V; Input 2 5.5 V; Output 1 5.5 V; Input 1 5.5 V; Output 2 5.5 V; Input 2 5.5 V; Output 1 5.5 V; Input 1 5.5 V; Output DD S3C72C8/P72C8 Min Typ Max 0.67 – – 1.5 1 0.48 – – 1.8 800 – – 650 3200 3800 325 – ...
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... S3C72C8/P72C8 Table 15-8. A.C. Electrical Characteristics (Continued – Parameter Symbol Output Delay for t KSO SCK to SO Interrupt Input INTH INTL High, Low Width RESET Input Low t RSL Width NOTE: Minimum value for INT0 is based on a clock of 2t CPU CLOCK 1 ...
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... Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 15-10 Symbol Conditions V – DDDR 1.8 V DDDR DDDR t – SREL Released by RESET t WAIT Released by interrupt S3C72C8/P72C8 Min Typ Max 1.8 – 5.5 – 0 – – – 17 – – ...
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... S3C72C8/P72C8 TIMING WAVEFORMS V DD Execution of STOP Instruction RESET Figure 15-2. Stop Mode Release Timing When Initiated By RESET V DD Execution of STOP Instruction Power-down Mode Terminating Signal (Interrupt Request) Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request Internal Reset Operation Stop Mode Data Retention Mode ...
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... ELECTRICAL DATA Figure 15-4. A.C. Timing Measurement Points (Except for 15-12 0 Measurement Points 0 1/ Figure 15-5. Clock Timing Measurement at X 1/fxt t XTL Figure 15-6. Clock Timing Measurement at XT S3C72C8/P72C8 0 0 and 0 0 XTH ...
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... S3C72C8/P72C8 TCL1 RESET INT0 INTP30, INTP31 Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts 1 TIL Figure 15-7. TCL1 Timing t RSL Figure 15-8. Input Timing for RESET t INTL 0.8 V 0.2 V ELECTRICAL DATA t TIH RESET Signal t INTH DD DD 15-13 ...
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... ELECTRICAL DATA SCK SI t KSO SO 15-14 t KCY SIK Input Data Output Data Figure 15-10. Serial Data Transfer Timing KSI 0 0 S3C72C8/P72C8 ...
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... S3C72C8/P72C8 16 MECHANICAL DATA OVERVIEW This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram #42 #1 0.50 ± (1.77) 1.00 ± NOTE: Dimensions are in millimeters. 42-SDIP-600 39.50 MAX 39.10 ± 0.2 0.1 1.78 0.1 Figure 16-1. 42-SDIP-600 Package Dimensions MECHANICAL DATA #22 #21 0-15 16-1 ...
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... MECHANICAL DATA #44 NOTE: Dimensions are in millimeters. Figure 16-1. 44-QFP-1010B Package Dimensions 16-2 13.20 ± 0.3 10.00 ± 0.2 44-QFP-1010B #1 + 0.10 0.35 - 0.05 0.80 (1.00) S3C72C8/P72C8 0-8 + 0.10 0.15 - 0.05 0.10 MAX 0.05 MIN 2.05 ± 0.10 2.30 MAX ...
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... It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72C8 is fully compatible with the S3C72C8, both in function and in pin configuration. Because of its simple programming requirements, the S3P72C8 is ideal for use as an evaluation chip for the S3C72C8. ...
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... P0.3/BTCO P0.2/SI P0.1/SO 17 OUT OUT Figure 17-2. S3P72C8 42-SDIP Pin Assignments S3C72C8/P72C8 COM2 42 COM3 41 COM4/SEG15 40 COM5/SEG14 39 COM6/SEG13 38 COM7/SEG12 37 SEG11/P7.3 36 SEG10/P7.2 35 SEG9/P7.1 34 SEG8/P7.0 33 SEG7/P6.3 32 SEG6/P6.2 31 SEG5/P6.1 30 SEG4/P6 SEG3/P5.3 SEG2/P5.2 27 SEG1/P5.1 26 SEG0/P5 ...
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... RESET RESET NOTE: Parentheses indicate pin number for 42-SDIP package. Table 17-2. Comparison of S3P72C8 and S3C72C8 Features Characteristic Program Memory Operating Voltage ( OTP Programming Mode Pin Configuration EPROM Programmability OPERATING MODE CHARACTERISTICS When 12 supplied to the V The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below ...
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... V ± 10% 6.0 MHz DD 4.19 MHz 6.0 MHz = 5 V 10% 4.19 MHz ± ± 10% 6.0 MHz DD 4.19 MHz = 3 V ± 10 ± 10% DD SCMOD = = 5 V ± 10% 0000B ± 10 ± 10% SCMOD = DD 0100B = 3 V ± 10% DD S3C72C8/P72C8 Min Typ Max – 3.0 8.0 2.3 5.5 1.5 4.0 1.0 3.0 1.3 2.5 1.2 1.8 0.5 1.5 0.44 1.0 – 15.0 30 5.0 15 2.5 5 0.5 3 0.2 3 0.1 ...
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... S3C72C8/P72C8 CPU CLOCK 1.5 MHz 1.05 MHz 0.75 MHz 15.6 kHz CPU CLOCK = 1/n x oscillator frequency ( 64 1.8 SUPPLY VOLTAGE (V) Figure 17-3 Standard Operating Voltage Range Main Oscillator Frequency (Divided MHz 4.2 MHz 3.0 MHz 6 7 S3P72C8 OTP 17-5 ...
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... S3P72C8 OTP 17-6 NOTES S3C72C8/P72C8 ...