mx25l12855e Macronix International Co., mx25l12855e Datasheet - Page 22

• Manufacturer Part Number: mx25l12855e
• Description: Secured Serial Flash
• Manufacturer: Macronix International Co.

MX25L12855E
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
sector is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array data
will be protected (no change) and the WEL bit still be reset.
(14) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see table 6) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI
→ CS# goes high. (see Figure 30)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
block is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array data
will be protected (no change) and the WEL bit still be reset.
(15) Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE32). Any address of the block (see table 6) is a valid address for
Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on
SI → CS# goes high.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
block is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array data
will be protected (no change) and the WEL bit still be reset.
(16) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (see
Figure 31)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
P/N: PM1466
REV. 0.05, MAR. 05, 2009
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