mx25l3255d Macronix International Co., mx25l3255d Datasheet - Page 18

• Manufacturer Part Number: mx25l3255d
• Description: Security Serial Flash
• Manufacturer: Macronix International Co.

P/N: PM1431
(5) Block Write Lock Protection (BLOCKP)
The BLOCKP instruction is for write protection a specified block of memory, using A23-A16 (A15-A0 don't care) ad-
dress bits to assign a 64Kbyte block to be protected as read only. This feature allows user to stop protecting the en-
tire block through the chip unprotect command (UNLOCK).
The WREN (Write Enable) instruction is required before issuing BLOCKP instruction.
The sequence of issuing BLOCKP instruction is: CS# goes low→send BLOCKP (E2h) instruction → send 3 address
bytes assign one block to be protected on SI pin → CS# goes high. (see Figure 13)
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
(6) Read Block Write Lock status (RDBLOCK)
The RDPLOCK instruction is for reading the status of permanent lock of a specified block, using A23-A16 (A15-A0
=0) address bits to assign a 64Kbyte block and read permanent lock status bit which the first byte of Read-out cycle.
The first byte data out DQ0 is"1" to indicate that this block has be locked permanently, that user can read only but
cannot write, program or erase this block permanently. The first byte data out DQ0 is "0" to indicate that this block
hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low→ send RDBLOCK (FBh) instruction→ send 3 ad-
dress bytes to assign one block on SI pin→ read block's protection lock status bit on SO pin → CS# goes high. (see
Figure 16)
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
Status Register
Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit
reserved
bit7
x
reserved
bit6
x
reserved
bit5
x
reserved
bit4
x
18
reserved
bit3
x
reserved
bit2
MX25L3255D
x
(write enable
0=not write
volatile bit
1=write
enable
enable
latch)
WEL
bit1
REV. 0.03, MAR. 13, 2009
0=not in write
progress bit)
operation
operation
volatile bit
(write in
1=write
WIP
bit0