lh5496 Sharp Microelectronics of the Americas, lh5496 Datasheet
lh5496
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lh5496 Summary of contents
Page 1
... PDIP 32-Pin PLCC Pin and Functionally Compatible with IDT7201 FUNCTIONAL DESCRIPTION The LH5496/96H are dual port memories with internal addressing to implement a First-In, First-Out algorithm. Through an advanced dual port architecture, they provide fully asynchronous read/write operation. Empty, Full, and Half-Full status flags are provided to prevent data over- flow and underflow ...
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... DUAL-PORT RAM WRITE READ ARRAY POINTER POINTER 512 DATA OUTPUTS FLAG FF LOGIC EXPANSION FL/RT LOGIC XO/HF XI Figure 3. LH5496/96H Block Diagram PIN XO/HF XI FL/ CMOS 512 9 FIFO OUTPUT R PORT CONTROL PIN TYPE * DESCRIPTION Expansion Out/Half-Full Flag O Expansion In I First Load/Retransmit ...
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... Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 3. Negative undershoots of 1 amplitude are permitted for once per cycle. OPERATING RANGE SYMBOL PARAMETER T Temperature, Ambient, LH5496 A T Temperature, Ambient, LH5496H A V Supply Voltage ...
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... LH5496/96H AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times (10% to 90%) Input Timing Reference Levels Output Reference Levels Output Load, Timing Tests 1,2 CAPACITANCE PARAMETER C (Input Capacitance (Output Capacitance) OUT NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25 with ...
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... XOL t Expansion Out HIGH XOH t Expansion In Pulse Width XI t Expansion In Recovery Time XIR t Expansion in Setup Time XIS NOTES: 1. LH5496 only. 2. All timing measurements performed at ‘AC Test Condition’ levels. 1 (Over Operating Range MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN ...
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... LH5496/96H OPERATIONAL DESCRIPTION Reset The device is reset whenever the Reset pin (RS) is taken to a LOW state. The reset operation initializes both the read and write address pointers to the first memory location. The XI and FL pins are also sampled at this time to determine whether the device is in Single mode or Depth Expansion mode ...
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... Figure 6. Asynchronous Write and Read Operation t RSC RRSS RSR t WRSS t EFL FFH HFH Figure 5. Reset Timing t t RPW VALID DATA OUT WPW VALID DATA IN LH5496/96H t RHZ VALID DATA OUT VALID DATA IN 5496-14 5496-5 7 ...
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... LH5496/96H TIMING DIAGRAMS (cont’d) LAST WRITE Figure 7. Full Flag from Last Write to First Read LAST READ NOTE: The Data Out pins ( are forced into high-impedance state whenever EF = LOW. Figure 8. Empty Flag from Last Read to First Write ...
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... Effective Write Pulse Width after Full Flag HIGH. WPF VALID DATA IN t WEF t t WLZ A Figure 9. Read Data Flow-Through t RFF t WFF VALID DATA OUT Figure 10. Write Data Flow-Through LH5496/96H t RPE t REF VALID DATA OUT t WPF VALID DATA IN 5496-8 5496-9 9 ...
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... LH5496/96H TIMING DIAGRAMS (cont’ NOTES RPE RPW Effective Read Pulse Width after Empty Flag HIGH. RPE 3. The Data Out pins ( are forced into high-impedance state whenever EF = LOW NOTES WPF WPW Effective Write Pulse Width after Full Flag HIGH. ...
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... XIS RTR . RTC Figure 14. Retransmit Timing t XOH Figure 15. Expansion Out Timing t XIR WRITE TO FIRST AVAILABLE LOCATION t XIS Figure 16. Expansion In Timing LH5496/96H 5496-13 READ FROM LAST VALID LOCATION t t XOL XOH 5496-15 READ FROM FIRST VALID LOCATION 5496-16 11 ...
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... Figure 18. FIFO Width Expansion (512 18) 12 Width Expansion Word-width expansion is implemented by placing mul- tiple LH5496/96H devices in parallel. Each LH5496/96H should be configured for standalone mode. In this ar- rangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. ...
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... ORing the FF pins of all devices and ORing the EF pins of all devices respectively. The Half-Full flag and Retransmit functions are not available in Depth Expan- sion mode LH5496/96H EF FF Vcc LH5496/96H FF EF Vcc LH5496/96H LH5496/96H R 9 DATA OUT EMPTY 5496-19 13 ...
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... EFa HFa RTa 14 LH5496/96H devices in parallel but opposite directions. The Data In pins of a device may be tied to the corre- sponding Data Out pins of another device operating in the opposite direction to form a single bidirectional bus inter- face. Care must be taken to assure that the appropriate read, write, and flag signals are routed to each system ...
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... MIN. 28-pin, 300-mil PDIP 15 13.45 [0.530] 12.95 [0.510] 14 0.30 [0.012] 0.20 [0.008] 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 28-pin, 600-mil PDIP LH5496/96H DETAIL 7.62 [0.300] TYP. 28DIP-1 DETAIL 15.24 [0.600] TYP. 28DIP-2 15 ...
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... MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT ORDERING INFORMATION LH5496/96H X Device Type Temperature Package Range * LH5496 only Example: LH5496U-25 (CMOS 512 x 9 FIFO, 32-pin PLCC, 25 ns) 16 1.27 [0.050] 4 SIDES BSC 11.51 [0.453] 11.35 [0.447] 12.57 [0.495] 12.32 [0.485] 2.41 [0.095] 1.52 [0.060] 10.92 [0.430] 0.38 [0.015] 9.91 [0.390] MIN ...