fx009a Consumer Microcircuits Limited, fx009a Datasheet - Page 4

• Manufacturer Part Number: fx009a
• Description: Low-noise Digitally Controlled Amplifier Array
• Manufacturer: Consumer Microcircuits Limited

The gain of each amplifier block (Channel 1 to Channel 8)
in the FX009A is set by a separate 8-bit data word ( bit 7
to bit 0 ). This 8-bit word, consisting of 4 Address bits (bit
7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded
to the Control Data Input in serial format using the external
data clock.
Data Loading
The 8-bit data word is loaded bit 7 first and bit 0 last.
Bit 7 must be a logic “1” to address the chip.
If bit 7 in the word is a logic “0” that 8-bit word will not be
executed. Figure 4 (below) shows the timing information
required to load and operate this device.
Table 1 Address Word Format
Fig.4 Serial Control Data Loading Diagram
Bit 7
MSB
Timing
t
Serial Clock "High" Pulse Width
t
Serial Clock "Low" Pulse Width
PWH
PWL
1
1
1
1
1
1
1
1
SERIAL DATA CLOCK
SERIAL DATA IN
LOAD/LATCH
LOAD/LATCH
(ONE 8-BIT WORD)
Bit 6
0
0
0
0
1
1
1
1
Bit 5
0
0
1
1
0
0
1
1
Logic ’1’
t
Loaded
DS
BIT 7
First
t
PWL
Bit 4
LSB
0
1
0
1
0
1
0
1
t
DH
t
PWH
Channel
Selected
1
2
3
4
5
6
7
8
t
Data Set-up Time
t
Data Hold Time
DS
DH
BIT 6
4
BIT 1
Data is loaded to the FX009A on the rising edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse. Table
1 shows the format of each 4-bit Address word, Table 2
shows the format of each Gain Control word with Figure 4
describing the data loading operation and timing.
Table 2 Gain Control Word Format
Bit 3
MSB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BIT 0
Bit2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Loaded Last
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
t
Load/Latch Delay
t
Load/Latch Pulse Width
t
Load/Latch Over Time
LSB
Bit 0
LLD
LLW
LLO
8th
Clock
Pulse
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
t
LLD
Powersave
(0.43dB)
Stage 1 to 7
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0.428
0.857
1.286
1.714
2.143
2.571
t
-3.0
LLW
3.0
0
Next
Clock
Pulse
Powersave
t
(2.0dB)
LLO
Stage 8
-14.0
-12.0
-10.0
10.0
12.0
14.0
-8.0
-6.0
-4.0
-2.0
2.0
4.0
6.0
8.0
0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB