act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 13

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

external agent read response for a system with a
transaction.
and the response data pattern is DDxxDD. Figure 9 shows
a processor block write where the processor was
programmed with write-back data rate boot code 2, or
DDxxD-Dxx.
Data Prefetch
prefetch (PREF) and floating-point data prefetch (PREFX)
instructions. These instructions are used by the compiler or
by an assembly language programmer when it is known or
suspected that an upcoming data reference is going to miss
in the cache. By appropriately placing a prefetch
instruction, the memory latency can be hidden under the
execution of other instructions. If the execution of a
prefetch instruction would cause a memory management or
address error exception the prefetch is treated as a NOP.
to specify the action taken by the instruction. The
instruction can operate normally (that is, fetching data as if
for a load operation) or it can allocate and fill a cache line
with zeroes on a primary data cache miss.
Enhanced Write Modes
the original R4000 write mechanism: Write Reissue and
Pipeline Writes. In write reissue mode, a write rate of one
write every two bus cycles can be achieved. A write issues
if WrRdy* is asserted two cycles earlier and is still
asserted during the issue cycle. If it is not still asserted then
the last write will reissue. Pipe-lined writes have the same
two bus cycle write repeat rate, but can issue one additional
write following the deassertion of WrRdy*.
External Requests
issued by an external device. These requests take one of
two forms: Write requests and Null requests. An external
device executes a write request when it wishes to update
one of the processors writable resources such as the internal
interrupt register. A null request is executed when the
external device wishes the processor to reassert ownership
Figure 7 shows a processor block read request and the
The read latency is 4 cycles (ValidOut* to ValidIn*),
The ACT 7000ASC supports the MIPS IV integer data
The “Hint” field of the data prefetch instruction is used
The ACT 7000ASC implements two enhancements to
The ACT 7000ASC can respond to certain requests
SCD7000A Rev B
SysClock
ValidOut*
Release*
SysCmd
ValidIn*
RdRdy*
WrRdy*
SysAD
Read
Addr
Figure 7 – Processor Block Read
nData
Data0
13
of the processor external interface. Typically a null request
will be executed after an external device, that has acquired
control of the processor interface via ExtRqst*, has
completed an independent transaction between itself and
system memory in a system where memory is connected
directly to the SysAD bus. Normally this transaction would
be a DMA read or write from the I/O system.
Test / Breakpoint Registers
processor
debugging, a pair of Test/Break-point, or Watch, registers,
Watch1 and Watch2,
ACT 7000ASC. Each Watch register can be separately
enabled to watch for a load address, a store address, or an
instruction address. All address comparisons are done on
physical addresses. An associated register, Watch Mask,
has also been added so that either or both of the Watch
registers can compare against an address range rather than
a specific address. The range granularity is limited to a
power of two.
in an exception. If the Watch is enabled for a load or store
address then the exception is the Watch exception as
defined for the R4000 with Cause exception code
twenty-three. If the Watch is enabled for instruction
addresses then a newly defined Instruction Watch
exception is taken and the Cause code is sixteen. The
Watch register which caused the exception is indicated by
Cause bits 25..24.
Watch1, 2 Store Load Instr
Watch
Mask
nData
Data1
Register
To increase both observability and controllability of the
When enabled, a match of either Watch register results
Table 9 summarizes a Watch operation.
Table 9 – Watch Control Register
thereby
63
62
easing
Mask
Data2 Data3
nData NEOD
31:2
Bit Field/Function
have
61 60:36
hardware
been
0
Watch
Mask
Addr
35:2
added to the
1
2
and
Watch
Mask
software
1:0
0
0
1