at1230 Arrive Technologies, Inc., at1230 Datasheet - Page 2

• Manufacturer Part Number: at1230
• Description: Oc-12/3 Pdh Mapper/adm
• Manufacturer: Arrive Technologies, Inc.

S
B
Please contact
US
© 2009 Arrive Technologies All Rights Reserved
S
B
OC-12/STM-4
OC-12/STM-4
OC-3/STM-1
Overwrite I/F
OH Output
Y
Y
L
L
622Mb/s/
622Mb/s
155Mb/s
Quad
Quad
S
O
S
O
4 OC-12/STM-4 Network Interface ports with on-chip CDR
4 individual OC-12/STM-4/OC-3/STM-1 ports with on-chip
CDRs
SONET/SDH Section/Line Overhead Processor
Hardware based Line and Path APS for SONET/SDH
SONET/SDH Line BER monitoring (10-3 to 10-9)
Full SONET/SDH TOH Transparency
STS/VC Pointer Processor with standard and random
concatenations
TU3 Pointer Processor
VT/TU Pointer Processor with standard and random
concatenations
Hi-order/Lo-order 511-channel POH processor pool
511-channel Tandem Connection Monitor pool
SONET/SDH Hi-order/Lo-order 511-channel BER monitor pool
(10-3 to 10-9)
Flexible TOH and POH Add/Drop port
336x336 STS/VC High Order Cross-connect
2688x2688 VT/TU Low Order Cross-connect
48x48 TU3 Cross-connect
8K DS0s and associated Signaling Cross-connect with 168/126
DS1/E1 slip buffers
512-channel HDLC pool of DCC, PDH Facility Data Link, CCS
channel, Local Data Link, and Redundancy Data Link
Clock synthesizer and system active/standby synchronizer
T
T
C
C
w
E
E
K
K
M
M
D
D
w
[e-mail]
F
F
I
I
BER Monitor
SONET/SDH
A
A
OC-12/3 PDH Mapper/ADM
Rev. 1.0 – Jan 2009
A
& PDH Line
A
POH BERT
E
E
Add/Drop
511 Hi/Lo
Monitor
SERDES/
G
SERDES/
G
Pool
T
A
Port
T
A
w
OH
Quad
Quad
CDR
CDR
1
1
R
T
R
T
2
2
U
U
A
A
.
3
3
R
R
M
M
0
0
E
E
Processor
511 Hi/Lo
Path OH
OC-48/12
STM-16/4
OC-48/12
STM-16/4
a
Framers
Framers
S
S
Pool
Quad
Quad
r
r
Processors
Processors
Connection
Cross-Connect
511 Hi/Lo
Tandem
TOH
TOH
Pool
2.5Gb/s
48x48
i
TU3
for further information.
v
Processor
Processor
Pointer
Pointer
ZBT RAM
e
Interface
External
SSRAM
ZBT
Aligner
t
TU3
e
Cross Connect
512 HDLC
Controller
Redundant
Datalink
Pool
17.5Gb/s
Local &
336x336
STS/AU
c
P
P
h
D
D
H
H
n
Aligner
Multiplexed 12 DS3/E3s, or 336 DS1s, or 252 E1s or any
mixed PDH bus
12 DS3 C-bit Parity and DS3 M13 multiplexing
12 E3 G.832 and E3 G.751 E13 multiplexing
Asynchronous mapping 12 DS3/E3 to 12 STS-1/VC-3 SPE
336 DS1 SF/ESF/SLC-96/DDS Framers supporting J1 and
SF/ESF
252 E1 basic frame or CRC-4 multi-frame framers
Synchronous/Asynchronous mapping 336/252 DS1/E1 to
VT1.5/VT2 (or TU-11/TU-12)
DS3/E3, DS1/E1 LCV-based BER monitoring (10-3 to 10-9)
PDH through path Jitter Attenuation
PDH transmultiplexing to/from SONET/SDH
VT/TU
Synthesizer
Clock/Sync
Clock/Synch
F
F
E
E
o
I/O
DS3/E3
Mapper
A
Async
A
SPE
l
T
T
Cross-Connect
U
U
Processor
o
2688x2688
Mapper/
R
Pointer
R
VT/TU
VT/TU
5Gb/s
Redundancy
Controller
E
E
Redundant
Control I/F
g
S
S
i
e
DS1/E1/J1
M13/E13
Framers
Framers
DS3/E3
Controller
s
JTAG I/F
Preliminary Short Data Sheet
JTAG
DS0 EXP Bus
Buffered
connect
8K x 8K
Cross-
.
DS0
c
PDH Mux
Interface
DS1/E1
DS3/E3
uP Bus I/F
Interface
o
uP
m
AT PDH Bus
VIETNAM
336 DS1s or
12 DS3/E3s
Subscriber
Multiplexed
Interface
252 E1s
DS0
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