at1212 Arrive Technologies, Inc., at1212 Datasheet - Page 2

• Manufacturer Part Number: at1212
• Description: Oc-12 Multi-service Adm
• Manufacturer: Arrive Technologies, Inc.

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© 2007 Arrive Technologies All Rights Reserved
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2 OC-12/STM-4 Network Interface ports with
on-chip CDR
4 individual OC-3/STM-1 ports with
on-chip CDR
1x622Mbps drop muxed port with
on-chip CDR for 9xEC-1
3 serial EC-1 ports with on-chip B3ZS
Encoder/Decoder
SONET/SDH Section/Line Overhead Processor
Hardware based Line and Path APS for
SONET/SDH
SONET/SDH Line BER monitoring
(10
Full SONET/SDH TOH Transparency
STS/VC Pointer Processor with standard and
random concatenations
TU3 Pointer Processor
VT/TU Pointer Processor with standard and
random concatenations
Hi-order/Lo-order 511-channel POH Processor
pool
511-channel Tandem Connection Monitor pool
SONET/SDH Hi-order/Lo-order 511-channel
BER monitor pool (10
Flexible TOH and POH Add/Drop port
135x135 STS/VC High Order Cross-connect
2100x2100 VT/TU Low Order Cross-connect
36x36 TU3 Cross-connect
8K DS0s and associated Signaling
Cross-connect
512-channel HDLC pool of DCC, PDH Facility
Data Link, CCS channel, Local Data Link, and
Redundancy Data Link
Clock synthesizer and system active/standby
synchronizer
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-3
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w
E
E
to 10
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K
M
M
D
D
w
Network
OC‐12/
622b/s
STM‐4
F
-9
side
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)
A
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OC-12 Multi-Service ADM
Rev. 1.3 – May 2008
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w
1
1
R
T
R
T
Interface
SDRAM
Mapper
DS3/E3
SDRAM
2
AGG
DDR
Async
2
SERDES
U
DDR2
U
SPE
A
A
84 DS1s or 63 E1s
DS1/E1 DS3/E3
Add/Drop Side
.
Mux Interface
1
Bulk PDH
1
Multiplexed
R
3 DS3/E3s
R
M
M
-3
PDH
2
2
E
E
to 10
Interface
SDRAM
SDRAM
VCAT
DS1/E1/J1
Processor
M13/E13
a
DDR
Mapper/
DDR2
Framers
Framers
Pointer
DS3/E3
VT/TU
S
S
Framers
OC‐12/
STM‐4
-9
r
)
SSRAM
ZBT RAM
Interface
External
ZBT
r
Subscriber
Processors
I/F
Cross‐Connect
DS0 Buffered
POH BERT
511 Hi/Lo
TOH
2100x2100
Monitor
connect
8K x 8K
Cross-
Aligner
Pool
VT/TU
VT/TU
i
Cross Connect
Ext DS0
v
I/F
Connection
511 Hi/Lo
Tandem
Processor
Pointer
Pool
e
D
D
Cross-Connect
Cross‐Connect
Controller
Redundant
512 HDLC
A
A
Datalink
t
Local &
Pool
Aligner
2 GbE ports with on-chip 1.25Gbps CDR
2 ESCON/DVB-ASI/FICON/Low-speed FC
(200/270/540Mbps) ports with serial
clock and data interface
8 Fast Ethernet ports via SMII or SS-SMII
OIF SPI-3 Interface up to 128 physical
ports with programmable data
segmentation of 64 or 128 bytes
Ethernet MAC controller with flow control
including jumbo frame
Support 802.3ah Ethernet OAM
processing and loopback
128 Hi/Lo-Order/PDH VCAT channels
Supports VCAT differential delay with up
to 256ms for Hi/Lo-Order, up to 384ms
for DS1s, up to 256ms for E1/E3s and
up to 217ms for DS3s
Supports LCAS with hitless add/remove
and fault isolation
GFP-T/F, PPP/HDLC, LAPS and ATM
encapsulation
TUG-3 (SDH concatenation with both
VC-4-Xv and VC-3-Xv) supported
Support EoS/EoPDH/EoPoS with or
without Data Aggregation
Traffic Aggregation and Management at
Layer 2 for VLAN/MPLS with Classifying,
Policing, Queuing, Shaping, and
Scheduling
Large DDR2 SDRAM for Packet Buffers
36x36
TU3
TU3
T
T
Cross Connect
A
A
e
Clock/Sync
Synthesizer
Clock/Synch
135x135
STS/AU
F
F
ASI/Low‐Speed
2 ESCON/DVB‐
I/O
E
FC ports
E
c
A
A
PCS
Controller
JTAG I/F
Lo‐order & PDH
T
h
T
JTAG
Map STS‐12
VCAT LCAS
OIF SPI‐3
U
U
HDLC/ATM Encapsulation
GFP‐T/GFP‐F/LAPS/PPP/
(VLAN/MPLS Processor)
OIF SPI‐3
Layer 2/3
Data I/F
Add/Drop Side
n
R
R
Processor
Interface
Pointer
Data AGG
Data
E
uP Bus
E
uP
I/F
Fast Ethernet
Octal SS‐
MII/SMII
o
S
S
ports
Ethernet MAC
8
Hi‐order VCAT
Map STS‐24
Redundancy
Controller
Redundant
Control I/F
LCAS
l
Processors
TOH
SERDESS
Dual
2 GbE
ports
o
Add/Drop
OH Output
Overwrite
Port
OH
I/F
g
OC-12/
Framers
STM‐4
i
Processor
511 Hi/Lo
Path OH
51M EC‐1s
Pool
Direct
Pointer Processor
3
SONET/SDH
SONET/SDH
e
Add/Drop Side
Processor
Framers
SONET/SDH
TOH
SONET/SDH &
PDH Line BER
4xOC-3/STM-1 or
SERDES
s
Monitor
Combinations
SERDES
Preliminary Short Data Sheet
QUAD
9xEC-1 or
P
P
D
D
.
multiplexing
Asynchronous mapping 3
DS3/E3 to 3 STS-1/VC-3 SPE
84 DS1 SF/ESF/SLC-96/DDS
Framers supporting J1 and
SF/ESF
63 E1 basic frame or CRC-4
multi-frame framers
Synchronous/Asynchronous
mapping 84/63 DS1/E1 to
VT1.5/VT2 (or TU-11/TU-12)
8064-DS0 Signaling
Processor for Signaling Scan
and Dial Pulse Collection
DS3/E3, DS1/E1 LCV-based
BER monitoring (10
PDH thru path Jitter
Attenuation
PDH transmultiplexing
to/from SONET/SDH
PDH VCAT and LCAS in
compliance with G.7043
Multiplexed 3 DS3/E3s,
or 84 DS1s, or 63 E1s
or any mixed PDH bus
3 DS3 C-bit Parity and
DS3 M13 multiplexing
3 E3 G.832 and E3 G.751 E13
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c
Network
622Mb/s
F
F
OC‐12/
STM‐4
side
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o
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m
U
U
R
R
E
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VIETNAM
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