ymf754 ETC-unknow, ymf754 Datasheet - Page 24

• Manufacturer Part Number: ymf754
• Description: Ds-1e
• Manufacturer: ETC-unknow

YMF754
4C-4Dh: D-DMA Slave Configuration
4E-4Fh: DS-1E Power Control 2
b0................CE: Channel Enable
b[2:1] ..........TS: Transfer Size
b3................EA: Extended Address
b[15:4] ........Base Address : D-DMA Slave Base Address
b0................CMCD: CODEC Master Clock Disable
b1................PSFM: Power Save FM Synthesizer
b2................PSSB: Power Save Sound Blaster
This bit enables the Distributed DMA function.
These bits indicate the size of the DMA transfer. Since DS-1E supports only 8-bit DMA transfer, the bits
are hardwired to 00b.
DS-1E does not support extended address mode. This bit is hardwired to 0b.
These bits indicate the D-DMA slave base address.
Setting this bit to “1” disables the oscillation of the CMCLK. To stop a clock, when the CMCLK is
supplied to the AC’97, it is required that b13:PR5 bit of 4A-4Bh register is set to “1”. (If the Secondary
AC’97 is used, it is also necessary that b5:SPR5 bit of 5A-5Bh register is set to “1”.)
Setting this bit to “1” stops a clock supplied to the FM synthesizer block.
Setting this bit to “1” stops a clock supplied to the Sound Blaster block.
b15
b15
“0”: Disable Distributed DMA
“1”: Enable Distributed DMA
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
-
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b14
b14
-
b13
b13
-
PSHWV
b12
b12
(default)
(default)
(default)
PSIO
b11
b11
PSACL PSDIR
Base Address
(default)
b10
b10
(Read Only)
(Read Only)
b9
b9
-24-
PSDIT
b8
b8
PSZV PSSRC PSPCA PSJOY PSMPU PSSB
b7
b7
b6
b6
b5
b5
b4
b4
EA
b3
b3
June 28, 1999
b2
b2
TS
PSFM
b1
b1
CMCD
CE
b0
b0