ymf744 ETC-unknow, ymf744 Datasheet - Page 12

• Manufacturer Part Number: ymf744
• Description: Ds-1s
• Manufacturer: ETC-unknow

YMF744B
06-07h: Status
b6................PER: Parity Error Response
b8................SER: SERR# Enable
b4................CAP: Capability
b8................DPD: Data Parity Error Detected
b[10:9] ........DEVT: DEVSEL Timing
b11..............STA: Signaled Target Abort
b12..............RTA: Received Target Abort
b13..............RMA: Received Master Abort
b14..............SSE: Signaled System Error
b15..............DPE: Detected Parity Error
DPE
This bit enables DS-1S responses to Parity Error.
This bit enables DS-1S to drive SERR#.
This bit indicates that DS-1S supports the capability register. This bit is read only. When 58-59h :
ACPI Mode register, ACPI bit is “0”, the bit is “1”. When ACPI bit is “1”, the bit is “0”.
This bit indicates that DS-1S detects a Data Parity Error during a PCI master cycle.
This bit indicates that the decoding speed of DS-1S is Medium.
This bit indicates that DS-1S terminates a transaction with Target Abort during a target cycle.
This bit indicates that a transaction is terminated with Target Abort while DS-1S is in the master memory
cycle.
This bit indicates that a transaction is terminated with Master Abort while DS-1S is in the master memory
cycle.
This bit indicates that DS-1S asserts SERR#.
This bit indicates that DS-1S detects Address Parity Error or Data Parity Error during a transaction.
b15
“0”: DS-1S ignores all parity errors.
“1”: DS-1S performs error operation when DS-1S detects a parity error.
“0”: Do not drive SERR#.
“1”: Drives SERR# when DS-1S detects an Address Parity Error on normal target cycle or a Data Parity
Read / Write Clear
Default: 0210h
Access Bus Width: 8, 16, 32-bit
Error on special cycle.
SSE
b14
RMA
b13
RTA
b12
STA
b11
(default)
b10
DEVT
(Read Only)
b9
-12-
DPD
b8
b7
-
b6
-
b5
-
CAP
b4
b3
-
February 3, 1999
b2
-
b1
-
b0
-