ymf781 Yamatake Corporation, ymf781 Datasheet - Page 9
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ymf781
Manufacturer Part Number
ymf781
Description
Apl-1 Automobile Sound Player-1
Manufacturer
Yamatake Corporation
Datasheet
1.YMF781.pdf
(14 pages)
YMF781
SCLKN
SDI
SRDYN
SDO
・Clock Sync Serial Interface
Conditions: T
SCLKN frequency (Serial transfer speed)
SCLKN High time
SCLKN Low time
SDI set-up time
SDI hold time
SDO output delay time
SDO output hold time (*1)
SRDYN output delay time (L→H) (*2)
Input Signals
except XI
XI
(*1) The last SDO output data is held until the next SCLKN falling edge is detected.
(*2) Time to the High level in synchronization with SCLKN, when the first 1 bit is transmitted or received.
The falling timing depends on the transmit/receive process of the internal Control CPU.
OP
= -40 to 85℃, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF
Item
T
T
R
XR
T
SOH
T
SOD
T
T
XH
SL
T
T
XFREQ
SIS
T
T
F
XF
T
SFREQ
1 / T
Symbol
T
T
T
T
T
T
T
SRDD
SOD
SOH
SIS
SIH
SH
SFREQ
SL
T
T
SIH
V
V
XL
IH
IL
T
= 0.75*VDD or 0.75*VDDC
= 0.25*VDD or 025*VDDC
T
SRDD
SH
Min.
220
220
110
75
0
Typ.
V
V
1
IH
IL
= 0.75*VDD
= 0.25*VDD
Max.
200
300
2
V
V
IH
IL
= 0.75*VDDC
= 0.25*VDDC
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
9