dq8051 Digital Core Design, dq8051 Datasheet - Page 7

• Manufacturer Part Number: dq8051
• Manufacturer: Digital Core Design

ALU – Arithmetic Logic Unit performs the arithme‐
tic and logic operations during execution of an
instruction. It contains accumulator (ACC), Pro‐
gram Status Word (PSW), (B) registers and related
logic such as arithmetic unit, logic unit, multiplier
and divider.
Opcode Decoder – Performs an instruction opcode
decoding and the control functions for all other
blocks.
Control Unit – Performs the core synchronization
and data flow control. This module is directly con‐
nected to Opcode Decoder and manages execution
of all microcontroller tasks.
Program Memory Interface – Contains Program
Counter (PC) and related logic. It performs the
instructions code fetching. Program Memory can
be also written. This feature allows usage of a
small boot loader loading new program into RAM,
EPROM or FLASH EEPROM storage via UART, SPI,
I2C or DoCD™ module. Program fetch cycle length
can be programmed by user. This feature is called
Program Memory Wait States, and allows core to
work with different speed program memories.
External Data Memory Interface ‐ Contains mem‐
ory access related registers such as Data Page High
(DPH), Data Page Low (DPL) and Data Pointer eX‐
tended (DPX) registers. It performs the External
Data Memory addressing and data transfers.
Memory read and write cycle length can be pro‐
grammed by user. It allows core to work with dif‐
ferent speed ram memories.
Synchronous eXternal Data Memory (SXDM) In‐
terface – contains XDATA memory access related
logic allowing fast access to synchronous memory
devices. It performs the external Data Memory
addressing and data transfers. This memory can be
used to store large variables frequently accessed
by CPU, improving overall performance of applica‐
tion.
Internal Data Memory Interface – Internal Data
Memory interface controls access into the internal
256 bytes memory. It contains 8‐bit Stack Pointer
(SP) register and related logic.
U N I T S S U M M A R Y
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User SFRs Interface – Special Function Registers
interface controls access to the special registers. It
contains standard and used defined registers and
related logic. User defined external devices can be
quickly accessed (read, written, modified) using all
direct addressing mode instructions.
Interrupt Controller – Interrupt control module is
responsible for the interrupt manage system for
the external and internal interrupt sources. It con‐
tains interrupt related registers such as Interrupt
Enable (IE), Interrupt Priority (IP), and (TCON) reg‐
isters.
I/O Ports – Block contains 8051’s general purpose
I/O ports. Each of port’s pin can be read/write as a
single bit or as an 8‐bit bus called P0, P1, P2, and
P3.
Power Management Unit – Block contains ad‐
vanced power saving mechanisms with switchback
feature, allowing external clock control logic to
stop clocking (Stop mode) or run core in lower
clock frequency (Power Management Mode) to
significantly
Switchback feature allows UART, and interrupts to
be processed in full speed mode if enabled. It is
very desired when microcontroller is planned to
use in portable and power critical applications.
DoCD™ Debug Unit – it’s a real‐time hardware
debugger provides debugging capability of a whole
SoC system. In contrast to other on‐chip debuggers
DoCD™ provides non‐intrusive debugging of run‐
ning application. It can halt, run, step into or skip
an instruction, read/write any contents of micro‐
controller including all registers, internal, external,
program memories, all SFRs including user defined
peripherals. Hardware breakpoints can be set and
controlled on program memory, internal and ex‐
ternal data memories, as well as on SFRs. Hard‐
ware breakpoint is executed if any write/read oc‐
curred at particular address with certain data pat‐
tern or without pattern. Two additional pins
CODERUN, DEBUGACS indicate the sate of the
debugger and CPU. CODERUN is active when CPU
is executing an instruction. DEBUGACS pin is active
when any access is performed by DoCD™ debug‐
ger. The DoCD™ system includes JTAG interface
and complete set of tools to communicate and
work with core in real time debugging. It is built as
reduce
power
consumption.