dq8051xp Digital Core Design, dq8051xp Datasheet - Page 4

• Manufacturer Part Number: dq8051xp
• Manufacturer: Digital Core Design

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core can be easy adjusted to requirements of dedi‐
cated application and technology. Configuration of
the core can be prepared by effortless changing
appropriate constants in package file. There is no
need to change any parts of the code.
Besides mentioned above parameters all available
peripherals and external interrupts can be ex‐
cluded from the core by changing appropriate
constants in package file.
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● Interrupts
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● DoCD™ debug unit
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The following parameters of the DQ8051XP
Second Data Pointer (DPTR1)
DPTR0 decrement
DPTR1 decrement
Data Pointers auto‐switch
Data Pointers auto‐update
Timing access protection
Power Management Mode
Stop mode
Peripherals
Synchronous XDM
FUCOM‐ compare
FCHS ‐ change sign
FABS ‐ absolute value
FSIN, FCOS‐ sine, cosine
FTAN, FATAN‐ tangent, arcs tangent
And more peripherals
C O N F I G U R A T I O N
All trademarks mentioned in this document are trademarks of their respective owners.
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subroutines
location
size
Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
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Comprehensible and clearly defined licensing
methods without royalty per chip fees make using
of IP Core easy and simply.
Single Site license option is dedicated for small and
middle sized companies making its business in one
place.
Multi Sites license option is dedicated for corpo‐
rate customers making its business in several
places. Licensed product can be used in selected
branches of corporate.
In all cases number of IP Core instantiations within
a project, and number of manufactured chips are
unlimited. The license is royalty per chip free.
There is no time of use restrictions.
There are two formats of delivered IP Core
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called HDL Source
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Source code:
VHDL & VERILOG test bench environment
Technical documentation
Synthesis scripts
Example application
Technical support
VHDL, Verilog RTL synthesizable source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
VHDL Source Code or/and
VERILOG Source Code or/and
FPGA netlist
Active‐HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Installation notes
HDL core specification
Datasheet
IP Core implementation support
3 months maintenance
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Delivery the IP Core updates, minor and ma‐
jor versions changes
Delivery the documentation updates
Phone & email support
D E L I V E R A B L E S
L I C E N S I N G