mu9c4485a Music Semiconductors, Inc., mu9c4485a Datasheet - Page 11

• Manufacturer Part Number: mu9c4485a
• Description: Wideport Lancam? Family
• Manufacturer: Music Semiconductors, Inc.

Select register to the value of the desired device’s Page
address and leaving /EC HIGH.
The Full Flag daisy chain causes only the device whose /FI
input is LOW and /FF output HIGH to respond to an
instruction using the Next Free address. After a reset, the
Next Free Address register is set to zero.
Status Register
The 32-bit Status register, shown in Table 12, is the default
source for Command Read cycles. Bit 31 is the internal Match
flag, which will go LOW if a match was found in this particular
device. Bit 30 is the internal Multiple Match flag, which will go
LOW if a Multiple match was detected. Bit 29 is the internal
Full flag, which will go LOW if the particular device has no
NOTES:
1.
2.
3.
4.
5.
6.
7.
Case
Case
6
6
1
2
3
4
5
1
2
3
4
5
Exceptions are:
If /MF is disabled in the Control register, /MA (Internal) is forced HIGH preventing a Case 6 response.
This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.
This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.
For a Command Read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain
(for example, /FI LOW and /FF HIGH) and NO if it does not.
This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.
This is NO if the Persistent Destination is Memory at Highest-Priority match.
2
2
A) A write to the Device Select register is always active in all devices;
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.
Internal
Internal
/EC(int)
/EC(int)
1
1
1
0
0
0
1
1
1
0
0
0
/MA (int)
/MA (int)
Internal
Internal
OPERATIONAL CHARACTERISTICS Continued
X
X
X
X
1
0
X
X
X
0
1
0
Table 6b: Enhanced Mode Device Select Response
Table 6a: Standard Mode Device Select Response
External
External
/MI
/MI
X
X
X
0
1
1
X
X
X
0
X
1
DS FFFFH and
Device Select
Device Select
and DS
DS = FFFFH
DS FFFFH
DS=FFFFH
DS = PA
DS=PA
DS PA
Reg.
Reg.
X
X
X
X
X
X
11
PA
empty memory locations. Bits 28 and 27 are the Skip and Empty
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Skip and Empty bits will read
11 until a read or move from memory has occurred. The rest of
the Status register contains the Page address of the device
and the address of the Highest-Priority match. After a reset or
a no-match condition, the match address bits will be all 1s.
Comparand Register (CR)
The 64-bit Comparand register is the default destination
for data writes and reads, using the Segment Control register
to select which of the two 32-bit segments of the Comparand
register is to be loaded or read out. The persistent source
and destination for data writes and reads can be changed
to the mask registers or memory by SPS and SPD
Command
Command
Write
Write
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
WidePort LANCAM
3,6
3,6
3
3
3
3
3
3
1
1
Data Write
Data Write
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
4,7
4,7
4
4
4
4
4
4
Command
Command
Read
Read
YES
YES
YES
NO
NO
YES
NO
NO
NO
NO
NO
NO
5
5
5
5
5
5
®
Family
Data Read
Data Read
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
Rev. 2