sh66k33a SinoWealth Micro-Electronics Corp. Ltd, sh66k33a Datasheet - Page 10

• Manufacturer Part Number: sh66k33a
• Description: Mask 1k 4-bit Micro-controller
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

8. Interrupt
Two interrupt sources are available on SH66K33A:
- Timer0 interrupt
- Port B & Port C or Port B & Port C & Port D rising edge detection interrupt (Code option)
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program.
These flags are cleared to “0” at initialization by chip reset.
System Register:
When IEx is set to “1” and the interrupt request is generated (IRQx is “1”), the interrupt will be activated and vector address will
be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are reset to “0” automatically, so when IRQx is “1” and IEx is set to “1” again, the interrupt will be activated and vector address
will be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Nesting:
During the CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing
sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the
instruction of execution N is IE enabled, then the interrupt will start immediately after the next two instruction executions.
However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be
terminated.
Timer Interrupt
The input clocks of Timer0 is based on system clock as Timer0 source. The timer overflow from $FF to $00 will generate an
internal interrupt request (IRQT0 = 1), If the interrupt enable flag is enabled (IET0 = 1), a timer interrupt service routine will start.
Timer interrupt can also be used to wake the CPU from HALT mode.
Port Rising Edge Interrupt
Only the input port can generate an external interrupt. The analog input cannot generate an interrupt request.
Any one of the I/O input pin transitions from GND to V
would not be able to make an interrupt request until all of the input pins have returned to GND. This can also be used to wake
the CPU from STOP mode.
Address
$00
$01
Inst. cycle
Bit3
-
-
Interrupt Generated
IRQT0
IET0
Bit2
Instruction
Execution
N
1
Bit1
-
-
Interrupt Servicing Sequence Diagram
Interrupt Accepted
Instruction
Execution
I1
2
IRQP
Bit0
IEP
DD
would generate an interrupt request. Further rising edge transition
10
R/W
R/W Interrupt enable flags
R/W Interrupt request flags
Vector Generated
Instruction
Execution
Stacking
I2
3
Fetch Vector address
Reset IE.X
4
Remarks
Start at vector
address
5
SH66K33A