sh66p51 SinoWealth Micro-Electronics Corp. Ltd, sh66p51 Datasheet - Page 29

• Manufacturer Part Number: sh66p51
• Description: Otp 2k 4-bit Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

10. Interrupt
Three interrupt sources are available on SH66P51:
- Timer0 overflow interrupt
- Base timer overflow interrupt
- Port’s falling edge detection interrupt (PBC)
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the
program. Those flags are cleared to “0” at initialization by the chip reset.
System Register:
When IEx is set to “1” and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address
will be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY
flag will be saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt
enable flags (IEx) are clear to “0” automatically, thus, when IRQx is 1 and IEx is set to “1” again, the interrupt will be
activated and vector address will be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Servicing Sequence Diagram:
Interrupt Nesting:
During the SH6610C CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt.
The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request
is ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the next two instruction
executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service
will be terminated.
Timer Interrupt
The input clock of Timer0 is based on system clock and the input clock of Base timer is based on OSC clock. The timer
overflow from $FF to $00 will generate an internal interrupt request (IRQT0 or IRQBT = 1), If the interrupt enable flag is
enabled (IET0 or IEBT = 1), a timer interrupt service routine will start. Timer interrupt can also be used to wake the CPU
from HALT mode.
Port Falling Edge Interrupt
Only the digital input port can generate a port interrupt. The analog input can not generate an interrupt request.
Any one of the I/O input pin transitions from VDD to GND would generate an interrupt request (IRQP = 1). Further falling
edge transition would not be able to make a new interrupt request until all of the input pins have returned to V
Interrupt can be used to wake the CPU from HALT or STOP mode.
Address
$00
$01
Inst. cycle
Bit3
-
-
Interrupt Generated
Instruction
Execution
IRQT0
IET0
Bit2
N
1
IRQBT
Interrupt Accepted
IEBT
Bit1
Instruction
Execution
I1
2
IRQP
Bit0
IEP
Vector Generated
29
Instruction
Execution
R/W
R/W
R/W
Stacking
I2
3
Interrupt enable flags
Interrupt request flags
Fetch Vector address
Reset IE.X
4
Remarks
Start at vector
address
5
SH66P51
DD
. Port