sh66l10a SinoWealth Micro-Electronics Corp. Ltd, sh66l10a Datasheet - Page 22

• Manufacturer Part Number: sh66l10a
• Description: 2k 4-bit Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

11. Watchdog Timer
The watchdog timer is a down-count counter, and its clock source is fetched from the system clock, so it will not run in the STOP
mode. The watchdog timer automatically generates a device reset when it overflows. It can be enabled or disabled permanently
by using the code option. To prevent it timing out and generating a device reset condition, users should write watchdog timer
reset bit ($1A Bit3) as “1” before timing-out.
System Register $1A
The WDT has a time-out period of more than 0.5ms (V
is desired, a prescaler with a division ratio of up to 1:1024 can be assigned to the watchdog timer under software control by
writing to the T0M register ($02 Bit2 - Bit0).
Prescaler Divide Ratio:
Notes:
If enabled by the code option, the Watchdog Timer will be cleared when the WDT bit is set in Power-On initial. The WDT bit will
be cleared only if the Watchdog Timer time-out occurs both in normal operation mode and in the HALT mode. The Watchdog
Timer is cleared when the device wakes up from the STOP mode, regardless of the source of wake-up.
Status and Condition
Program Notes:
1. If the system clock is changed by the code option, the time-out period of the Watchdog Timer will also fix at approx. 0.5ms.
2. The WDT can use a prescaler with a division ratio of up to 1:2048 to prolong the time-out periods by writing to the T0M
Address
register. Since the T0M register is shared with Timer0, the WDT has the same prescaler value as Timer0. If T0M register is
changed for some proper use, the WDT’s time-out period will also be changed.
$1A
T0M.2
WDT
1
1
1
1
0
0
0
0
1
0
0
1
1
WDT
Bit 3
Power-On reset
WDT cause reset during normal operation
WDT cause reset in HALT mode
Pad reset during normal operation or in HALT mode
Pad reset or interrupt wake-up in STOP mode
(32.768kHz CRY)
T0M.1
131kHz RC/
SYSTEM
1/4 OSC
CLOCK
1
1
0
0
1
1
0
0
Bit 2
T0M.0
Bit 1
1
0
1
0
1
0
1
0
(0.122ms)
0.030ms/
Bit 0
Condition
SCALER_1
Internal
1/16/(4)
Prescaler divide ratio
1:1
1:2
1:4
1:8
1:32
1:128
1:512
1:1024 (Power on initial)
R/W
R/W Bit3: Watchdog timer reset/flag register (Write 1 to reset WDT)
DD
= 1.5V 131kHz RC or 32.768kHz Crystal). If a longer time-out period
out Period 0.488ms
22
WDT Time
/1
/2
/4
Time out period
PRESCALER
/8
Final WDT
TM0
Remark
/32 /128
Timer-out period
0.5ms
1.0ms
2.0ms
4.0ms
16.0ms
64.0ms
256.0ms
512.0ms
/512 /1024
SH66L10A