ut62256c ETC-unknow, ut62256c Datasheet - Page 5

• Manufacturer Part Number: ut62256c
• Description: Power Cmos Sram
• Manufacturer: ETC-unknow

Rev. 1.0
WRITE CYCLE 1
WRITE CYCLE 2
Notes :
1.
2. A write occurs during the overlap of a low CE and a low WE .
3. During a WE controlled with write cycle with OE LOW, t
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
6. t
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
TEL: [phone]
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
Address
Address
CE
D
WE
WE
D
OUT
D
to turn off and data to be placed on the bus.
D
CE
WE or CE must be HIGH during all address transitions.
OW
OUT
IN
outputs remain in a high impedance state.
IN
and t
CE LOW
WHZ
are specified with C
UTRON
t
AS
(
(
t
AS
CE
WE
FAX: [phone]
transition occurs simultaneously with or after
Controlled)
Controlled)
(4)
t
WHZ
(4)
L
= 5pF. Transition is measured ± 500mV from steady state.
(1,2,3,5)
(1,2,5)
t
t
AW
CW
t
WHZ
32K X 8 BIT LOW POWER CMOS SRAM
t
AW
t
t
WC
CW
t
t
WP
t
WP
WC
5
High-Z
WP
High-Z
t
DW
must be greater than t
Data Valid
t
DW
Data Valid
t
DH
t
WR
t
OW
t
WR
WE LOW
t
DH
WHZ
UT62256C
+t
DW
to allow the drivers
transition, the
(4)
P80027