sii1161 Silicon image, sii1161 Datasheet - Page 38

• Manufacturer Part Number: sii1161
• Description: Panellink Receiver
• Manufacturer: Silicon image

STAG_OUT#
Voltage Ripple Regulation
The power supply to VCC pins is very important to the proper operation of the receiver chips. Two examples of
regulators are shown in Figure 23 and Figure 24.
SiI-DS-0096-D
EQ_DATA
DEV_REV
Register
VND_IDH
DEV_IDH
OCK_INV
VND_IDL
DEV_IDL
ZONEO
Name
CKST
LBW
ST
Access
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
Default
0x01
0x00
0x00
0x00
0x00
0xD
00
1
0
0
1
0
Figure 23. Voltage Regulation using TL431
Table 19: I
Vendor ID Low Byte
Vendor ID High Byte
Device ID Low Byte
Device ID High Byte
Device Revision Byte
Equalization Setting. All settings are valid. For non DVI-compliant transmitters,
stronger equalization may be necessary even for shorter cables.
0000 = Most equalization (long cables)
:
1101 = Moderate equalization (default)
:
1111 = Least equalization (short cables)
Data and Sync Output Drive Strength
0 = Low-Drive
1 = High-Drive (default)
Clock and DE Output Drive Strength
0 = High-Drive (strength is 2X that of Data and Sync -default)
1 = Low-Drive (strength is equal to that of Data and Sync)
ODCK Polarity
0 = Normal polarity (default)
1 = Inverted polarity
Staggered Data Bus Outputs
0 = Staggered
1 = Non-staggered (default)
Bandwidth of the PLL:
00 = 4MHz (default)
01 = 3MHz
10 = 6MHz (often the best setting for non DVI-compliant transmitters)
11 = 5MHz
Zone Output – indicates current operating zone
0 = Operating in zone optimized for lower frequencies
1 = Operating in zone optimized for higher frequencies
Vin=5V
3K Ω 1%
1K Ω 1%
2
C Register Field Definitions
34
Vout=3.3V
Description
TL431
SiI 1161 PanelLink Receiver
Data Sheet