ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 34

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD
FIELD
7:6
5:3
2
1
0
7
6
5
4
3
2
1
0
AX88796 L
RD2,RD1
PS1,PS0 PS1,PS0 : Page Select
START START :
NAME
NAME
STOP
OVW
,RD0
RDC
CNT
TXE
RXE
PRX
TXP
RST
PTX
The two bits selects which register page is to be accessed.
RD2,RD1,RD0 : Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88796 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address is not restored to the starting address if the
Remote DMA is aborted.
TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
This bit is used to active AX88796 operation.
STOP : Stop AX88796
This bit is used to stop the AX88796 operation.
Reset Status :
CR.
NOTE: This bit does not generate an interrupt, it is merely a status indicator.
Remote DMA Complete
Set when remote DMA operation has been completed
This bit is cleared by writing a “1”.
Counter Overflow
This bit is cleared by writing a “1”.
OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
This bit is cleared by writing a “1”.
Transmit Error
This bit is cleared by writing a “1”.
Receive Error
This bit is cleared by writing a “1”.
Packet Transmitted
This bit is cleared by writing a “1”.
Packet Received
Indicates packet received with no error.
This bit is cleared by writing a “1”.
Set when MSB of one or more of the Tally Counters has been set.
RD2 RD1 RD0
Set when AX88796 enters reset state and cleared when a start command is issued to the
Set when packet transmitted with one or more of the following errors
Indicates that a packet was received with one or more of the following errors
Indicates packet transmitted with no error
0
0
0
0
1
PS1
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
0
0
Excessive collisions
FIFO Underrun
0
0
1
1
X
PS0
0
1
0
1
X
0
1
3-in-1 Local Bus Fast Ethernet Controller
Not allowed
Remote Read
Remote Write
Not allowed
Abort / Complete Remote DMA
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DESCRIPTION
DESCRIPTION
ASIX ELECTRONICS CORPORATION