ax88190 ASIX Electronics Corporation, ax88190 Datasheet - Page 8

• Manufacturer Part Number: ax88190
• Description: Pcmcia 10/100m Fast Ethernet Mac Controller
• Manufacturer: ASIX Electronics Corporation

2.2 EEPROM Signals Group
EECS
EECK
EEDI
EEDO
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
Tab - 3 MII interface signals group
SIGNAL
SIGNAL
AX88190
I/O/PU
TYPE
TYPE
I/PU
O
O
O
O
O
O
I
I
I
I
I
I
I
PIN NO.
PIN NO.
90 – 87
99 – 96
106
107
108
109
85
83
82
86
84
95
94
92
91
PCMCIA Fast Ethernet MAC Controller
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
8
ASIX ELECTRONICS CORPORATION
DESCRIPTION
DESCRIPTION