ch7021a Chrontel, ch7021a Datasheet

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ch7021a

Manufacturer Part Number
ch7021a
Description
Sdtv Hdtv Encoder
Manufacturer
Chrontel
Datasheet

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Features
† Patent number 5,781,241
¥ Patent number 5,914,753
209-0000-032
Chrontel
Intel Proprietary.
VGA to SDTV/EDTV/HDTV conversion supporting
HDTV support for 480p, 576p, 720p, 1080i and
1080p
Support for NTSC, PAL, SECAM color modulation.
Macrovision
SDTV
Macrovision
progressive scan TV (480p, 576p)
CGMS-A support for SDTV and HDTV
High-speed SDVO
differential RGB inputs
Flexible TrueScale
overscan compensation in all SDTV/EDTV and
HDTV output resolutions †¥
Text enhancement filter in scan conversion¥
Adaptive de-flicker filter with up to 7 lines of
filtering in scan conversion¥
Contrast/Brightness/Sharpness control for TV output.
Hue/Saturation Control for TV output.
Support for SCART connector
Support for HDTV D-Connector
Outputs CVBS, S-Video, RGB and YPbPr
Support for VGA RGB bypass
TV / Monitor connection detect
Programmable power management
Four 10-bit video DAC outputs
Three sets of DAC outputs supporting SDTV /
HDTV / CRT RGB connectors
Fully programmable through serial port
Configuration through Intel® SDVO OpCode
Complete Windows driver support
Offered in a 64-pin LQFP package
graphics resolutions up to 1600x1200
TM
TM
Rev. 1.0,
CH7021A SDTV / HDTV Encoder
7.1.L1 copy protection support for
copy protection support for
TM
(1G~2Gbps) AC-coupled serial
rendering engine supports
3/21/2005
General Description
The CH7021A is a Display Controller device which accepts
a digital graphics input signal, and encodes and transmits data
through analog SDTV ports (analog composite, s-video, RGB
or YPrPb) or an analog HDTV port (YPrPb). The device is
able to encode the video signals and generate synchronization
signals for NTSC, PAL and SECAM SDTV standards, as
well as analog HDTV interface standards and graphics
standards up to UXGA. The device accepts one channel of
RGB data over three pairs of serial data ports.
The TV-Out processor will perform scaling to convert VGA
frames to supported SDTV and HDTV output standards.
Adaptive de-flicker filter provides superior text display. Large
numbers of input graphics resolutions are supported up to
1600 by 1200 with full vertical and horizontal overscan
compensation in all output standards. A high accuracy low
jitter phase locked loop is integrated to create outstanding
video quality.
In addition to scaling modes, bypass modes are included
which perform color space conversion to SDTV or HDTV
standards and generate and insert SDTV or HDTV sync
signals, or output VGA style analog RGB for use as a CRT
DAC.
Different analog video connectors are supported including
composite, s-video, YPrPb, SCART, D-connector and VGA
connector.
Content protection support is provided for Macrovision
SDTV and EDTV modes. CGMS-A is also provided up to
1080i resolution.
Brief Datasheet
CH7021A
TM
in
1

Related parts for ch7021a

ch7021a Summary of contents

Page 1

... Rev. 1.0, 3/21/2005 General Description The CH7021A is a Display Controller device which accepts a digital graphics input signal, and encodes and transmits data through analog SDTV ports (analog composite, s-video, RGB or YPrPb analog HDTV port (YPrPb). The device is able to encode the video signals and generate synchronization ...

Page 2

... SDVO_B(+,-) Serial to Parallel 2 PLL Control 3 NTSC/PAL/ SECAM Encoder Scaling Scan Conv Flicker Filt HDTV Encoder RGB, Bypass Figure 1: Functional Block Diagram 209-0000-032 CH7021A Serial AS Port SPC Control SPD RESET* SC_DDC SD_DDC SC_PROM SD_PROM CVBS, S-Video, RGB, YPbPr CVBS DAC DAC 2 ...

Page 3

... SC_DDC 4 SD_PROM 5 SC_PROM 6 DVDD 7 RESET DGND 10 DGND 11 SPD 12 SPC 13 DVDD 14 BSCAN VDAC2 209-0000-032 Rev. 1.0, 3/21/2005 Chrontel CH7021 Figure 2: 64-Pin LQFP Package CH7021A 48 DL3 47 DL2 46 DL1 45 AGND_TVPLL2 44 TVCLK- 43 TVCLK+ 42 AVDD_TVPLL2 41 AVDD_TVPLL1 XI/FIN 38 AGND_TVPLL1 37 DGND 36 VSYNC 35 DVDD 34 CHSYNC 33 V5V 3 ...

Page 4

... DAC Output B Video Digital-to-Analog outputs. Refer to section Error! Reference source not found. for information regarding supports for Composite Video, S-Video, SCART, YPrPb and RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly terminated load. 209-0000-032 CH7021A ◊ Rev. 1.0, 3/21/2005 ...

Page 5

... Differential Clock Input associated with SDVO Data channel (SDVO_R+/-, SDVO_G+/-, SDVO_B+/-) The range of this clock pair is 100~200MHz. For specified pixel rates in specified modes this clock pair will run at an integer multiple of the pixel rate. Refer to section Error! Reference source not found. for details. CH7021A 5 ...

Page 6

... AGND_TVPLL2 TV PLL2 Ground 52,58,64 Power AVDD 49,55,61 Power AGND 33 Power V5V 6 Description Digital Supply Voltage (2.5V) Digital Ground DAC Supply Voltage (3.3V) DAC Ground DAC Supply Voltage (3.3V) DAC Ground DAC Supply Voltage (3.3V) DAC Ground (2.5V) (2.5V) Analog Supply Voltage (2.5V) Analog Ground D-Connector Supply Voltage (5V) 209-0000-032 CH7021A Rev. 1.0, 3/21/2005 ...

Page 7

... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 209-0000-032 Rev. 1.0, 3/21/2005 .008" SYMBOL 0.17 1.35 0.05 0.50 1.00 0.27 1.45 0.15 CH7021A BOTTOM VIEW K K EXPOSED PAD 0.45 0.09 0° 5.85 0.75 0.20 7° ...

Page 8

... Lead Free LQFP with 64 exposed pad Lead Free LQFP with exposed pad in Tape & 64 Reel Chrontel 2210 O’Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7021A Voltage Supply 2.5V & 3.3V 2.5V & 3.3V 2.5V & 3.3V 2.5V & 3.3V 209-0000-032 Rev. 1.0, 3/21/2005 ...

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