ch7005c Chrontel, ch7005c Datasheet - Page 37

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ch7005c

Manufacturer Part Number
ch7005c
Description
Digital Pc To Tv Encoder With Macrovisiontm
Manufacturer
Chrontel
Datasheet

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CHRONTEL
PLL Control Register
The following PLL and memory controls are available through the PLL control register:
MEM5V
PLL5VA
PLL5VD
PLLS
PLLCAP
PLLCPI
201-0000-025 Rev. 2.9, 6/24/2004
Bit:
Symbol:
Type:
Default:
7
MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the
memory supply is 3.3 volts.
PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is
used when the phase-locked loop analog supply is 3.3 volts.
PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when
the phase-locked loop digital supply is 3.3 volts (default).
PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL
supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL
supply) PLLS should be 0, and five stages are used.
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs.
Mode is shown below
PLLCHI controls the charge pump current of the PLL. The default value should be used.
6
5
PLLCPI
R/W
0
4
PLLCAP
R/W
0
3
PLLS
R/W
1
2
PLL5VD
0
R/W
Symbol: PLLC
Address: 20H
Bits: 6
1
PLL5VA
R/W
1
CH7005C
0
MEM5V
R/W
0
37

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