ch7013a Chrontel, ch7013a Datasheet - Page 29

• Manufacturer Part Number: ch7013a
• Description: Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
.
The Clock Mode Register also contains the following bits:
Start Active Video Register
This register sets the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The
entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position
overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and
511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading edge of sync to the first
active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading edge
of sync to the first active data must be a multiple of three clocks.
Position Overflow Register
This position overflow register contains the MSB values for the SAV, HP, and VP values, as follows:
201-0000-041 Rev. 1.5, 9/1/2004
Table 22. Input Data Format Register
XCM[1:0]
00
00
00
01
01
01
1X
1X
1X
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
• MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the
• M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the
• CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the
• VP8 (bit 0) is the MSB of the vertical position value (see explanation under “Vertical Position Register”).
negative edge, one selects the positive edge.
14.31818MHz clock is used as a frequency reference to the PLL . In slave mode (0) the XCLK input is used
as a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are
forced to one.
subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the
subcarrier to free-run, and should be used when the ACIV bit is set to one.
7
SAV7
R/W
0
7
Reserved
R/W
0
PCM[1:0]
00
01
1X
00
01
1X
00
01
1X
6
SAV6
R/W
0
6
Reserved
R/W
0
XCLK
1X
1X
1X
2X
2X
2X
3X
3X
3X
5
SAV5
R/W
0
5
Reserved
R/W
1
P-OUT
1X
2X
3X
1X
2X
3X
1X
2X
3X
4
SAV4
R/W
0
4
Reserved
R/W
1
Input Data Modes Supported
0, 1, 2, 3, 4, 5, 7, 8, 9
0, 1, 2, 3, 4, 5, 7, 8, 9
0, 1, 2, 3, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
6
6
6
3
SAV3
R/W
0
3
Reserved
R/W
0
2
SAV2
R/W
0
2
SAV8
R/W
0
Symbol: SAV
Address: 07H
Bits: 8
Symbol: PO
Address: 08H
Bits: 3
1
SAV1
R/W
0
1
HP8
R/W
0
CH7013A
0
SAV0
R/W
0
0
VP8
R/W
0
29